Sanjay G (sanjaypersonal2007)
VLSI Design Student | Aspiring Physical Design & ASIC Realization Engineer | Cadence • Verilog • STA • RTL to GDSII |Ex-Intern @ ENNOVI |
VLSI Design Student | Aspiring Physical Design & ASIC Realization Engineer | Cadence • Verilog • STA • RTL to GDSII |Ex-Intern @ ENNOVI |
