WaferYield AI Autonomous Wafer Diagnostic Agent

Inspiration

Semiconductor manufacturing yield excursions cost billions and suffer from severe diagnostic bottlenecks. The inspiration behind WaferYield AI was to eliminate the traditional "Physical Congestion Trap"—where automated layout generation fails at high core utilization limits—by building an intelligent, closed-loop agentic system that automates root-cause analysis, DRC-clean Verilog patching, and 8D reporting without human latency.

What it does

WaferYield AI operates as an autonomous wafer diagnostic agent that ingests manufacturing telemetry (such as Lot LOT_WM811K_99), traces multi-tool failures across equipment like Etch Chamber 4 and CMP Polisher 3, and executes closed-loop physical self-correction. It transitions layout constraints from a failing congestion state (98% core utilization) to a successful, DRC-clean signoff (55% core utilization with synthesized Verilog compensation patches). All results and executive summaries are rendered through an interactive 4-tab dashboard hosted on Hugging Face Spaces.

How we built it

LLM / Agentic Orchestration: Powered by Gemini 3.5 Flash for primary supervision and structured Pydantic EightDReport generation, working alongside specialized worker models (Kimi K3 for Vision and ASIC Design, and Inkling for RCA) hosted via Fireworks. Physical Design & Verification: Integrated an OpenLane and ASIC EDA flow abstraction layer to simulate the RTL-to-GDSII physical design loop, mocking routing congestion and verifying parameter-relaxed signoff. Frontend Portal: Built using a vanilla HTML5, CSS3, and JavaScript single-page architecture featuring custom view panes, an interactive tabbed interface (8D Portal, Autonomous Loop, Architecture & Flow, Raw JSON), and raw JSON inspectors. Hosting & Deployment: Deployed directly onto Hugging Face Spaces (uttarasawant/xprize_wafer_analysis) to host static application assets, HTML report renderers, and execution logs.

Challenges we ran into

Managing multi-model orchestration across distributed inference workers to ensure structured data parsing for complex 8D reports.

Simulating the physical design feedback loop to cleanly handle and recover from high-density routing congestion errors (98% utilization limits) without breaking downstream verification scripts.

Synchronizing real-time telemetry logs with a clean, responsive single-page web interface.

Accomplishments that we're proud of

Successfully engineering a fully closed-loop agentic workflow that transitions a failing semiconductor layout to a DRC-clean state autonomously. Integrating multi-pass agent telemetry into a polished, production-ready 4-tab interactive dashboard on Hugging Face Spaces. Achieving robust structured output validation using Pydantic models with Gemini 3.5 Flash and specialized worker models.

What we learned

The power of combining high-level supervisory reasoning (Gemini 3.5 Flash) with domain-specific tool execution loops for complex hardware design flows.

How dynamic constraint relaxation (such as shifting core utilization thresholds) acts as an effective automated strategy to bypass traditional physical congestion traps in EDA pipelines.

What's next for WaferYield AI Autonomous Wafer Diagnostic Agent

Scaling the simulated OpenLane pipeline to ingest real-world, full-scale GDSII layouts and multi-layered foundry datasets.

Expanding the agent's autonomous patch-generation capabilities to handle multi-corner timing closure and advanced node-specific lithography constraints.

Enhancing the dashboard with real-time streaming telemetry and expanded multi-lot comparative analytics.

Built With

• asic
• autocorrection
• defect
• frontiermodels
• inkling
• kimik3
• semiconductor