VeriVision

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  Problem vs Solution

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  Custom AST & Regex Parser workflow

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  Real-time RTL Schematic Engine & Logic diagram generation.

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  Static Linter and AI Auto-Fix code comparison.

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  Cloud Architecture & SaaS CI/CD Pipeline flow chart

Inspiration 💡

Hardware engineering and FPGA/ASIC design often come with steep learning curves and fragmented debugging tools. Traditional EDA simulation suites are bulky, expensive, and lack real-time interactive visual feedback. Students, hobbyists, and digital logic developers often struggle to visualize how their hardware description code (Verilog) translates into actual gate-level logic flow or AST representations. Furthermore, catching subtle code smells—such as unused wires or blocking assignment issues—early in the development cycle is critical to prevent costly downstream synthesis failures.

We created VeriVision Pro to bridge this gap by offering a lightweight, cloud-friendly, interactive EDA Playground and AI-assisted verification engine.

What it does ⚙️

VeriVision Pro is an open-source, web-based RTL visualizer and static analysis suite built specifically for Verilog hardware designers. Key features include:

• Real-time RTL Schematic Visualization: Parses Verilog HDL on-the-fly and dynamically generates interactive logic flow graphs using Graphviz rendering engines.
• Static Analysis & Linting: Scans code for common synthesis pitfalls, unused signals, undeclared variables, and code smells without needing heavy synthesis toolchains.
• AI Error Assistant & Code Fixer: Provides instantaneous AI recommendations and structured feedback to fix hardware design bugs on the spot.
• Hardware AST & Symbol Inspection: Extracts module signatures, input/output counts, wire vectors, and complete hierarchical symbol trees for rapid debugging.

How we built it 🛠️

• Frontend UI: Designed with Python and Streamlit for a responsive, modern web application layout.
• Custom Syntax & AST Engine: Built custom AST extraction rules using Python regex parsing engines to tokenize module parameters, port directions, internal wire vectors, and conditional assignment logic.
• Diagram Rendering Engine: Integrated the Graphviz visualization pipeline to plot left-to-right digital circuit logic diagrams directly from parsed AST trees.
• Code Intelligence: Structured static linter routines and integrated AI explanation modules to flag blocking/non-blocking assignment mismatches and suggest real-time auto-fixes.

Challenges we ran into 🏃‍♂️

• Regex AST Parsing Complexity: Tokenizing nested Verilog constructs (like ternary multiplexer statements and variable vector ranges) without relying on heavy C++ synthesis backends was challenging. We solved this by designing custom modular regex rules to extract wire interconnectivity accurately.
• Dynamic Schematic Layout: Formatting Graphviz nodes and ports to cleanly mirror EDA schematic conventions required careful node-attribute mapping and node styling.
• UI Responsiveness: Ensuring the Streamlit interface remained snappy while performing live AST compilation and generating high-resolution diagram outputs in real-time.

Accomplishments that we're proud of 🏆

• Built a lightweight, fully functional EDA playground substitute that runs seamlessly in the browser.
• Successfully translated abstract Verilog HDL code blocks into crisp, readable digital logic diagrams in milliseconds.
• Integrated dynamic AI recommendations with static code linting to lower the barrier for digital logic engineering students and makers.

What we learned 📚

• Deepened our understanding of Hardware Description Language (HDL) parsing, Abstract Syntax Trees (AST), and compiler design fundamentals.
• Mastered dynamic graph-rendering techniques using Graphviz alongside Python data structures.
• Gained hands-on experience in building scalable, user-centric hardware verification software.

What's next for VeriVision Pro 🚀

• SystemVerilog & VHDL Support: Expanding the AST parser to handle full SystemVerilog logic structures and VHDL syntaxes.
• CI/CD Integration: Packaging the linter as a GitHub Action for automated pull-request verification in FPGA design pipelines.
• Interactive Circuit Simulation: Adding real-time logic vector testbench execution and waveform visualizers (VCD plotters) directly within the web app.

Built With

• digital-logic
• eda
• fpga
• graphviz
• python
• streamlit
• verilog