Inspiration
Hardware verification is one of the most time‑consuming and error‑prone parts of digital design. Writing testbenches, running simulations, and debugging waveforms often takes longer than writing the RTL itself. I wanted to explore whether an AI agent, powered by Gemini 3 and structured through the Agent Client Protocol (ACP), could automate this entire loop and give hardware engineers a faster, more intelligent way to validate their designs.
What it does
Verilog‑TestBench‑ACP‑Agent reads a Verilog module, generates a complete testbench, runs Icarus Verilog simulation, extracts waveform data, and validates behavior automatically. The agent uses Gemini 3 for reasoning and ACP for deterministic tool orchestration, enabling a fully automated, auditable verification workflow.
How we built it
The system is built around an ACP‑compliant agent that uses a tool manifest (tools.json) to call modular handlers for linting, file operations, simulation, diffing, and waveform extraction. Gemini 3 performs high‑level reasoning, while Icarus Verilog (iverilog + vvp) executes the actual simulation. The agent iterates through a generate → simulate → analyze → refine loop until the design validates cleanly.
Challenges we ran into
Coordinating multi‑step reasoning with deterministic tool calls required careful ACP schema design. Parsing VCD waveforms reliably was another challenge. Ensuring the agent could refine testbenches and apply diffs safely also required thoughtful iteration.
Accomplishments that we're proud of
We built a fully automated verification pipeline that can understand RTL, generate testbenches, run simulations, and interpret waveforms—all without human intervention. The modular ACP design makes the system extensible and audit‑ready.
What we learned
We learned how powerful Gemini 3 becomes when paired with structured tool orchestration. ACP provides the discipline needed for predictable agent behavior, while Gemini handles the reasoning and interpretation that traditional EDA tools cannot.
What's next for Verilog‑TestBench‑ACP‑Agent
Next steps include adding Verilator support, generating coverage metrics, handling multi‑module designs, integrating formal verification, and building a web UI for interactive debugging.
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