VeriFlow

Inspiration

The growing demand for fine-tuned large language models (LLMs) across industries inspired us to envision a seamless pipeline that enables businesses to fine-tune and deploy powerful models like Mistral Large 2 directly within their data platform, removing the need for external infrastructure. This project aims to bridge the gap between data management and advanced AI by integrating cutting-edge tools into a single ecosystem.

What it does

The VeriFlow is a Verilog generator automates the generation of high-quality Verilog RTL (Register Transfer Level) code for hardware design. It uses a large language model (LLM) to translate design descriptions into functional Verilog code, significantly improving efficiency in circuit design.

How we built it

1. Data Preparation: The design descriptions were paired with corresponding Verilog implementations, primarily generated with GPT-3.5's powerful text-to-code capabilities. It created a dataset with over 27,000 samples, each with a design description and corresponding Verilog code solution.

2. Model Fine-Tuning: Fine-tuned the Mistral Large 2 model within the container, and introducing a new training scheme incorporating code quality scoring, where candidate outputs were ranked for quality.

3. Deployment:

   • Saved the fine-tuned model to Snowflake stages for easy access.
   • Created a Snowflake SQL function to interact with the model, enabling seamless integration with other Snowflake workflows.

Challenges we ran into

Data Availability: A major challenge was the lack of publicly available, high-quality datasets for RTL code generation tasks. Model Performance and Quality: Generating Verilog code that is not only syntactically correct but also satisfies the functional requirements described in the design instructions was difficult. The challenge was to outperform existing solutions like GPT-3.5 in terms of accuracy and functionality for RTL tasks.

What's next for VeriFlow

VeriFlow aims to revolutionize the design and automation of Verilog modules by evolving into a comprehensive AI-driven solution for hardware design. Integrate VeriFlow with popular Electronic Design Automation (EDA) tools to streamline the verification, synthesis, and simulation workflows directly from the generated code. Fine-tuning the model using custom datasets from industry partners to ensure it stays updated with the latest design standards, best practices, and innovative use cases.

Built With

• cortex-search
• mistral-large2
• python
• snowflake
• snowpark-container-services
• streamlit