VERIDOC-AI

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  As you scroll, the hero animates from a clean headline into a live ‘analysis-in-progress’ view

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  Multiple language translation option for documentation

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  Option for select the verilog file and start analysis part.

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  Detailed report, with a Download Result button at the top that lets you quickly download the file for fast access.

Inspiration

VERIDOC-AI was inspired by the pain of debugging Verilog projects where subtle issues only appear at synthesis or on hardware, wasting hours of lab time for students and FPGA developers. It aims to give ALU and datapath designers an instant "code review plus lab TA" that explains problems in plain language instead of cryptic tool logs.

What it does

VERIDOC-AI analyzes uploaded Verilog files and generates a human-readable report that highlights:

1)Logical issues

2)Synthesis pitfalls

3)Hardware-specific risks (like long combinational paths or resource overuse)

It also suggests concrete fixes and optimizations, such as:

1)Using synchronous arithmetic

2)Pipelining strategies

3)Better numeric handling

Users can quickly download the analysis as a report with a single click. Example Verilog code that VERIDOC-AI can analyze:

module alu (
    input [7:0] a, b,
    input [2:0] op,
    output reg [7:0] result
);
    always @(*) begin
        case(op)
            3'b000: result = a + b;
            3'b001: result = a - b;
            3'b010: result = a & b;
            default: result = 8'b0;
        endcase
    end
endmodule

How we built it

We built a web app that takes Verilog source as input, parses the code, and feeds structured signal- and module-level information into Gemini 3 for deep reasoning about design patterns and edge cases.

The frontend provides an IDE-like experience with:

📊 Analysis view with real-time feedback

💾 Download Result button for instant report export

⚡ Antigravity code editor for seamless Verilog input and syntax highlighting

Tech Stack Integration:

Google Whisk for rapid prototyping and visual workflow orchestration

Google Flow to manage complex data pipelines between code parsing, AI analysis, and report generation

The backend orchestrates: code upload → static checks → prompt construction → report generation

This creates a smooth end-to-end verification experience.

Challenges we ran into

A major challenge was getting reliable, hardware-aware feedback instead of generic code comments, especially for timing-related issues like:

⚠️ Combinational loops

⚠️ Large dividers causing timing violations

⚠️ Bit-growth in arithmetic operations

We had to carefully design prompts and parsing logic so the AI could reason about:

Signed arithmetic: ( \text{result} = a \times (-b) )

Bit-growth calculations

Corner cases (division by zero, negative display handling)

Without hallucinating non-existent signals. ​

Accomplishments that we're proud of

We're proud that VERIDOC-AI can spot non-trivial hardware problems, such as:

🔍 Unsafe for-loops in dividers

🔍 Truncation in display paths

🔍 Misuse of shifts in multipliers

And then explain them in clear natural language.

We're also happy that the tool proposes actionable optimization strategies:

Synchronous operators

Pipelining techniques

BCD conversion

Making it useful both for learning and for real FPGA design iterations. ​

What we learned

We learned how powerful AI becomes when you combine it with structured static analysis instead of treating code as plain text, especially for HDL where small mistakes can break timing or synthesis.

Key insight: AI Quality=f(Structure,Context,Domain Knowledge)

We also learned how important developer experience is: simple touches like a clean report layout and one-click downloads significantly improve how often people actually use the tool in their workflow.

What’s next for VERIDOC-AI

Next steps for our roadmap:

🔮 Waveform-aware guidance - Upload simulation logs for deeper analysis 📝 Lint-style inline comments - Direct annotations in Verilog files 🌐 More HDL support - VHDL, SystemVerilog, Chisel 🔧 FPGA toolchain integration - Direct connection to Vivado, Quartus 🚀 CI/CD Pipeline integration - Continuous "design copilot" that runs on every commit

Demo: Check out our live deployment at https://veridoc-ai-gamma.vercel.app

Built With

• gemini
• github
• javascript
• lingo.dev
• next.js
• node.js
• react
• supabase
• tailwind
• typescript
• vercel