The Cortex Node

An ESP32 cognitive-capture digital twin that transforms a physical interrupt and microphone input into a private, explainable graph of human thought.

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Inspiration

Thoughts disappear surprisingly quickly. By the time someone unlocks a phone, opens an application, and decides where an idea belongs, the original thought may already be incomplete or gone.

As an electrical engineering student interested in embedded systems, algorithms, and intelligent devices, I wanted to approach this as a hardware problem. What if capturing a thought felt more like triggering an interrupt than writing a note?

The Cortex Node is a proposed physical cognitive-capture device built around an ESP32, an I2S microphone, a button, and a status LED. Pressing the button initiates an immediate capture event. Instead of creating another isolated recording, the system converts the input into a structured memory node and connects it with related ideas.

The project extends an earlier software-only cognitive-graph concept. For VoltHacks, I developed the embedded-device architecture, interactive hardware digital twin, GPIO and microphone simulation, serial protocol, firmware, and wiring specification.

What it does

The Cortex Node demonstrates how a dedicated embedded device could capture and organize fleeting thoughts.

The interactive prototype includes:

  • A simulated ESP32-WROOM-32
  • A virtual GPIO capture button
  • Simulated INMP441 microphone telemetry
  • Device power and status feedback
  • A 115200-baud serial packet monitor
  • An explainable six-stage cognitive pipeline
  • A searchable archive of captured thoughts
  • A graph generated from stored memories and their calculated relationships
  • ESP32 Arduino firmware and a wiring specification

Pressing the virtual hardware button generates a simulated GPIO interrupt packet and places an unfinished thought into the capture buffer. The thought then moves through six visible stages:

  1. Capture receives the input.
  2. Extract identifies significant concepts.
  3. Store creates a persistent local memory node.
  4. Score compares it with existing thoughts.
  5. Rank orders the strongest relationships.
  6. Visualize updates the cognitive graph.

The system stores thoughts locally in the browser. It does not transmit personal thought content to a remote database or external AI service.

The hardware interface is currently a digital twin. All displayed microphone readings and hardware packets are explicitly simulated. The physical circuit has not yet been assembled or validated.

How I built it

I divided the project into an embedded-device layer and a cognitive-graph layer.

The target embedded architecture uses:

  • ESP32-WROOM-32
  • INMP441 I2S microphone
  • Momentary push button
  • Status LED and resistor
  • GPIO interrupts
  • Serial communication

The repository includes Arduino C++ firmware for detecting a capture-button interrupt, controlling status feedback, and emitting structured serial events. It also includes a wiring specification for the proposed microphone, button, and LED circuit.

Because the physical circuit was not assembled during this prototype cycle, I created a browser-based hardware digital twin. The simulator models device power, changing microphone levels, button interrupts, GPIO assignments, and serial capture packets. It clearly identifies this information as simulated telemetry.

The cognitive application was built with Next.js, React, TypeScript, CSS, and SVG. Browser Local Storage provides private persistence.

Concept extraction uses deterministic text preprocessing. The system normalizes the input, removes common stop words, and selects significant terms. It then calculates connections using shared extracted concepts and meaningful word overlap.

The implemented relationship score is:

w(i,j) = 20 + 24K(i,j) + 12W(i,j)

K represents the number of shared extracted concepts. W represents meaningful shared words, capped at four. If two thoughts have no meaningful overlap, the system creates no connection.

This approach makes each graph relationship reproducible and explainable. The graph, connection count, density, concepts, and recurring themes are calculated from actual stored data rather than fabricated telemetry.

Challenges I ran into

The largest challenge was converting an abstract idea about preserving thought into a concrete engineering architecture.

I first had to define the boundary between the embedded device and the cognitive application. An ESP32 is well suited for button interrupts, microphone sampling, feedback, and packet creation. Graph construction, search, and visualization are more appropriate for a capable local client. Separating these responsibilities made the design more technically realistic.

Another challenge was making the digital twin functional rather than decorative. The virtual button needed to create a real state transition, produce a serial event, update the capture buffer, and initiate an observable processing flow. Likewise, the cognitive graph needed to represent stored thoughts and calculated connections instead of a predetermined animation.

I also had to maintain clear implementation boundaries. Although I had access to the proposed components, I did not physically assemble and validate the device during this development cycle. I therefore labeled every hardware reading as simulated and separated implemented software behavior from future physical validation.

Accomplishments that I'm proud of

I am proud that The Cortex Node connects embedded-system design with a working interactive application.

The completed prototype includes:

  • A functional ESP32 hardware digital twin
  • Simulated button-interrupt behavior
  • Simulated I2S microphone telemetry
  • Structured serial capture packets
  • A documented GPIO pin map
  • Arduino firmware
  • A physical wiring specification
  • A persistent and searchable memory archive
  • Explainable connection scoring
  • A data-driven cognitive graph
  • Responsive desktop and mobile interfaces

I am particularly proud that the project remains technically transparent. Judges can distinguish which components are implemented, which hardware behaviors are simulated, and which capabilities are planned for future physical development.

What I learned

I learned that a meaningful digital twin must model interfaces and state transitions, not merely resemble a physical device.

Designing The Cortex Node strengthened our understanding of hardware/software partitioning. The embedded device should remain focused on reliable capture, local sensor handling, feedback, and communication. The client application can then perform more complex organization and visualization without overloading the microcontroller.

I also learned that explainability is an architectural decision. Using deterministic concept extraction and relationship scoring makes it possible to show exactly why two thoughts are connected. A more complex model might eventually improve semantic understanding, but a transparent baseline is easier to test, reproduce, and trust.

Finally, I learned the importance of distinguishing a simulation from a physical result. A digital twin can still demonstrate valuable engineering behavior, but only when its assumptions and limitations are communicated clearly.

What's next for The Cortex Node

The immediate next step is assembling and validating the physical device.

I plan to:

  • Connect the ESP32, INMP441 microphone, button, resistor, and status LED
  • Flash and test the included firmware
  • Measure button-to-capture latency
  • Measure the microphone noise floor
  • Replace simulated packets with real ESP32 communication through Web Serial
  • Add a short local audio buffer
  • Implement voice activity detection
  • Add local or explicitly enabled speech-to-text
  • Encrypt stored cognitive data
  • Add user-controlled export and deletion
  • Experiment with on-device embeddings for stronger semantic connections
  • Design a battery-powered enclosure and custom PCB

A future Cortex Node could become a user-owned cognitive peripheral: one physical action for capturing a thought, private processing for organizing it, and a transparent interface for understanding how ideas develop over time.

The current submission is an implementation-ready hardware digital twin. Its cognitive pipeline and simulator are functional, while its firmware and wiring design provide a clear path toward a physically validated prototype.

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