Team Clock Work Gang_hardware

Inspiration

High-frequency trading firms use FPGAs because hardware reacts faster and more predictably than software. We wanted to see what it takes to build a real trading signal entirely in logic: no CPU, no operating system, just gates and flip-flops reacting to every price tick.

What it does

Our Tang Nano 20K receives 8-byte price packets over UART for two assets (Item A and Item B). For each asset, it keeps a rolling window of the last 16 prices and its moving average. When the price crosses above its average it signals BUY; when it crosses below, SELL; otherwise it repeats its last signal. It answers every request with an 8-byte response, and all parsing, state, and computation happen on the FPGA.

The averages use floor division by 16, implemented as a 4-bit right shift:

$$\text{avg} = \left\lfloor \frac{1}{16}\sum_{i=0}^{15} p_i \right\rfloor = \text{sum} \gg 4$$

A BUY fires when

$$p_{\text{prev}} \le \text{avg}{\text{old}} \;\land\; p{\text{now}} > \text{avg}_{\text{new}}$$

and a SELL fires on the mirror condition.

How we built it

HDL: VHDL, synthesized and placed with Gowin EDA.
UART: a custom receiver and transmitter at 115200 baud, 8N1
Packet logic: an 8-byte request parser and a response builder that echoes the index and item IDs in the same slot order
Per-item engines: a 16-price window, a 20-bit rolling sum updated as sum − oldest + newest, and a crossing detector that holds the last action
Session handling: index 0 resets all state, and indices 0–15 fill the window before any signal is evaluated

Challenges we ran into

The USB-serial bridge: the board's BL616 chip can drop bytes if responses are sent back-to-back, so we added idle time between response bytes and tuned it against latency.
Exactness: the scoring is bit-exact, so details like floor vs. rounding, the warm-up window, and routing by item ID rather than slot position all had to be precisely right.
Resource usage: we worked to keep the design small, since LUT count is part of the score.

What we learned

We learned a lot of how to think as a team and how to work with FPGAs.

Results

LUTs: 298 (reference: 542)
Robust test: 84/84 packets correct, average latency 16.638 ms

Final GitHub Submission

Repository: https://github.com/17vs/GatorQuantHacks Final Commit SHA: 7d5068cfe110a6e7cf18e6740acb9f2356d5e7da

AI disclosure

Claude supported project planning, and ChatGPT helped draft and refine the VHDL code. Our team built, programmed, and tested the FPGA design on the provided hardware.