Inspiration
ASIC idea suggested by advisor Robert Radway
What it does
Implements part of a graphics pipeline
How we built it
Mix of Cadence and open source software
Challenges we ran into
Software issues, chip DRC/DFM errors
Accomplishments that we're proud of
Custom standard cell library, utilizing industry VLSI software, taping out
What we learned
Openlane and Cadence tools, VLSI architecture, chip design
What's next for Team 7 - ARC (Accelerated Rasterizer Chip)
Tapeout 2
Built With
- cadence
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