Full Demo Video

Demo Video


This project explores decreasing FPGA compilation time. FPGAs, or Field Programmable Gate Arrays, provide an array of programmable logic that essentially allows hardware to be designed and programmed like software and are gaining popularity in high performance computing areas such as machine learning, computer vision, and video processing. However, FPGA compile times are REALLY long (on the order of hours to days) which discourages further adoption of the technology, and limits design space exploration.

Current work has demonstrated compilation time speedups by separating the compiled logical operators into physical partitions, and linking them with a packet switched network. We aim to extend this further by providing tooling and implementations of logical operators as RISC-V softcores. This will provide a fast compile-to-firmware pathway that will allow testing hardware accelerator code in a more realistic environment before an actual hardware compile.

What is the Problem?

  • FPGA compile times are long
  • REALLY LONG (on the order of hours to days)
  • Hardware designers would like to develop for hardware like we’re used to for software
  • Design, Compile, Debug, Iterate
  • This is not feasible with current state of compile times
  • Discourages innovation, limits the exploration space of accelerated solutions
  • Same problem, different people:
  • Hobbyists have a hard time getting into the FPGA space
  • Current solutions are costly, time consuming, and difficult to use
  • Want to allow all types of users to make a smooth transition from pure software to a hardware accelerated platform

Proposed Solution?

  • Automatically generate RISC-V softcores and firmware as stepping stone between software a hardware
  • Tooling for optimizing compile speed vs. optimizing performance
  • RISC-V cores will provide a streaming interface for high speed connection to other softcores and hardware modules with a Network-on-Chip
  • Can optimize one operator at a time for hardware while always having a working version
  • Allows separate compilation and linking of software and hardware

Why is this Solution Innovative

Traditional hardware compiles are monolithic and give few ways to trade off optimizations for compilation speed

  • This solution brings configuration experience from the software world
  • Why can’t building circuits have -O0, -O1, -O3 options?
  • Also from software world: Separate linking
  • Why can’t we build smaller circuits once, and only rebuild the ones that change?
  • Applying software solutions to hardware development
  • Allows more accurate results and larger datasets than RTL emulation
  • Provides distributed RISC-V softcores to run software instead of running on one high performance processor
  • Offers more parallelism than a single high performance processor
  • Softcores are spatially located in the same way as the final hardware operators

Status (5/3/2021)

  • Controller functional with Network-on-Chip
  • Integrated into prior automation work
  • Leaves fully functional with Network-on-Chip and controller
    • Still requires Network-on-Chip to memory converter for full automation and integration

Built With

  • c
  • c++
  • litex
  • migen
  • picorv32
  • python
  • spinalhdl
  • symbiflow
  • verilog
  • vexriscv
  • vivado
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