SPARSE CONNECTIVE EVENT DRIVEN CNN ACCELERATOR

\section*{Event-Driven CNN Accelerator for Real-Time Object Detection}

\begin{tabular}{|p{3cm}|p{11cm}|} \hline \textbf{Section} & \textbf{Details} \ \hline

\textbf{Inspiration} & Inspired by inefficiencies in frame-based CNN accelerators and research platforms like Eyeriss, the goal was to eliminate redundant computation by processing only meaningful visual events instead of full image frames. \ \hline

\textbf{What I Learned} & Gained deep understanding of event-driven hardware design, sparse dataflow architectures, FSM-based control, FPGA timing optimization, and latency--power trade-offs. Learned that reducing computation $O(N) \rightarrow O(k)$ is more effective than simply increasing parallelism. \ \hline

\textbf{How I Built It} & Designed a scalable $4 \times 2$ event-driven PE cluster architecture with event queues, routers, GLB memory, and layer controllers. Implemented RTL in Verilog and validated on Xilinx ZCU102 using Vivado. Developed a Python GUI for real-time event streaming via UART. \ \hline

\textbf{Key Innovation} & Early-decision event routing, sparse activation storage, event-aware processing elements, and handshake-based asynchronous communication (Valid/Ready). Reduced redundant memory access and switching activity. \ \hline

\textbf{Performance Impact} & Achieved $< 2.5$ ms latency, $< 5$W power consumption, and up to $40\times$ speedup compared to CPU-based inference. Processes only $10$--$20\%$ of data instead of full frames. \ \hline

\textbf{Challenges Faced} & Handling asynchronous events without loss, managing variable-length sparse data, achieving FPGA timing closure, and designing model-specific control FSMs. \ \hline

\textbf{Future Work} & Automatic PE scaling, advanced event filtering, neuromorphic sensor integration, and ASIC implementation for ultra-low-power edge AI deployment. \ \hline

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