SmartCells

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  A randomly generated grid of logic gate cells

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  An XOR gate implemented using fundamental logic gates

Inspiration

We spent four hours fully exploring different sources of inspiration. We carefully and deeply studied things that interested us like cellular automata, evolution simulators, morphogenesis, computation machines, and more. We believe that this process of exploring different topics paid off well, and it gave rise to our unique hackathon project, SmartCells.

What it does

We implemented a random boolean network (RBN) maker which consists of grid cells representing logic gates. Cells have binary states (0 or 1). Each cell takes input from 1 or 2 of its 8 neighboring cells (or itself). The cell will also have a type of gate associated with it (NOT, AND, OR, IS, INACTIVE, or ON). Every timestep, the cells will update their values based on value of their input cells and the gate operation they perform.

This RBN system is meant to challenge the user to implement their own more complex systems using the fundamental gates provided. The restriction of only taking input from adjacent cells makes this task considerably more difficult than traditional logic gates, which serves as an excellent, fun, and challenging puzzle exercise to improve the user's general understanding of logic gates and computation. Examples of systems we created so far using SmartCells include an XOR gate and a visually appealing loop of IS gates.

How we built it

• Uses C++ with SFML graphics
• Started with a robust grid system, then implementing Cell functionality of taking input from neighboring cells and performing a logical gate computation.
• Developed a command-line editing system to debug, modify, add, and delete cells as well as a file saving and loading system.
• Culminated in the careful design of a XOR network using the native AND, NOT, OR, and 'IS' gates.

Challenges

There were many times when we faced stealthy logic errors that weren't initially obvious. To combat these errors, we used a systematic engineering-style debug process where we diagrammed our network on paper and carefully identified how and where the errors were coming from in our program.

Accomplishments that we're proud of

• When faced with hidden logical errors, we first improved the usability of the project by creating a robust command line system to then accurately identify and debug errors.
• The file saving and loading feature allows users to save their work and pick up from where they left off, drastically improving the learning process.
• We were able to make an XOR network at the end of our project, which was challenging due to the unique restriction of cells only being able to take input from immediate neighbors.

What we learned

• Putting restrictions on a system to rule out problems is a great way to solve them.
• Taking a logical and ordered approach to solving problems in code instead of making hasty changes is truly the way to go when debugging.

Future plans

Our original plan included implementing a genetic algorithm to automatically evolve and perform simple computations and even control simple virtual organisms, but time constraints limited this goal. Pairing SmartCells with a genetic algorithm would have firmly classified this as an artificial intelligence project, as the RBN is basically an easily modifiable computation machine - with an added benefit of freeform recursive connections which allow for memory of past states. However, this currently remains a TODO and will be pursued sometime later in the future.

Requirements:

• Helps improve quality of life?
  • Serves as a cool sandbox puzzle game that is intellectually challenging, educational, and very fun.
• People interaction or systems interaction?
  • Allows people to freely interact with logical circuits and learn about computability.
• Ai/machine learning/computer vision/generative models?
  • If paired with genetic algorithms, it could be trained for certain computations or interesting tasks
• Novel?
  • Introduces a new type of neural network using binary values, logic gates, and recurrent freeform connections.

Built With

• c++
• sfml