SiliconPilot

SiliconPilot: Autonomous RTL Analysis, Repair, and Verification About the Project What inspired us? Digital hardware development requires precision. Even a small mistake in Verilog or SystemVerilog can introduce compilation errors, incorrect sequential behavior, unintended latches, or functional failures.

Engineers often spend considerable time identifying these problems, modifying RTL code, running lint tools, and repeating verification cycles.

I wanted to build an autonomous engineering system that could go beyond simply detecting errors. My goal was to create a system capable of analyzing RTL, understanding diagnostics, selecting appropriate repair strategies, modifying the source code, and verifying the results using real hardware design tools.

That vision led to SiliconPilot. How we built it SiliconPilot is an autonomous RTL engineering system developed using Python, Streamlit, Verilator, and Icarus Verilog.

The system follows an end-to-end engineering workflow:

1. RTL Analysis: Analyzes uploaded Verilog/SystemVerilog code and runs Verilator lint.
2. Diagnostic Classification: Identifies sequential assignment problems, width mismatches, latch risks, undriven signals, and coding-style issues.
3. Repair Strategy Selection: Selects appropriate repair strategies based on detected diagnostics.
4. Automated RTL Repair: Applies targeted modifications to the source code.
5. Iterative Verification: Re-runs lint analysis to evaluate whether repairs resolved the detected problems.
6. Functional Simulation: Uses Icarus Verilog when a compatible testbench is available.
7. Final Reporting: Reports verification results and highlights issues that still require engineering review. The architecture includes an RTL Diagnostics Engine, Diagnostic Classification, Strategy Executor, Iterative Repair Loop, Verified Repair Workflow, Batch Benchmark Runner, and Streamlit Interface.

We implemented repair strategies for sequential assignment correction, width mismatch handling, latch-risk reduction, undriven signal handling, conservative unused-signal cleanup, and missing combinational default assignments.

We also developed cross-platform tool execution to support Windows through WSL and Linux-based cloud deployment. Challenges we ran into One of our biggest challenges was ensuring that repaired RTL was not only lint-clean but also functionally correct.

During testing, we encountered a design that could pass lint but still fail functional simulation because a combinational output did not have a proper default assignment.

To address this, we improved the repair workflow by implementing a missing-combinational-defaults safety pass and ensuring that functional simulation runs after lint errors are cleared, even when non-fatal review warnings remain.

Another challenge was supporting different execution environments. The application needed to work locally on Windows while also running in a Linux-based cloud environment. We addressed this by separating HDL tool execution from the core diagnostic and repair logic.

We also focused on making repairs conservative and targeted to avoid introducing new problems while modifying existing RTL. Accomplishments that we're proud of We are proud of developing a working end-to-end RTL repair and verification system and successfully deploying it as a public Streamlit application.

Controlled benchmark results:

• 16/16 designs successfully repaired.
• 16/16 passed Verilator lint.
• 16/16 passed functional simulation.
• 16/16 achieved fully verified repair status. Unseen benchmark results:
• 6/6 designs passed functional simulation.
• 4/6 achieved completely lint-clean results.
• 2/6 passed simulation with no lint errors but retained non-fatal interface-review warnings. We also successfully demonstrated the public application using two example designs.

Broken ALU demonstration:

• Initial diagnostics: 3 errors and 4 warnings.
• Final diagnostics: 0 errors and 0 warnings.
• Verilator lint: PASS.
• Icarus Verilog simulation: PASS. Broken FSM demonstration:
• Initial diagnostics: 1 error and 2 warnings.
• Final diagnostics: 0 errors and 0 warnings.
• Verilator lint: PASS.
• Icarus Verilog simulation: PASS. Both demonstrations successfully completed the repair and verification workflow.

These results represent performance on the tested designs and do not establish universal RTL repair accuracy. What we learned Building SiliconPilot taught us that autonomous hardware engineering requires more than generating or modifying code.

A reliable RTL repair system must understand diagnostic context, apply appropriate modifications, rerun engineering tools, and evaluate functional behavior.

We learned that:

• Passing lint does not always guarantee functional correctness.
• Functional simulation is essential for evaluating repaired RTL.
• Automated modifications must be conservative and targeted.
• Unseen test designs are important for evaluating repair strategies.
• Cross-platform tool integration is essential for practical engineering software.
• Verification reports must distinguish fully successful repairs from designs that still require human review. Most importantly, we learned that an RTL repair is not complete simply because the source code has changed. Its outcome must be tested. What's next for SiliconPilot? Our next goal is to expand SiliconPilot into a more capable autonomous hardware engineering assistant.

Planned improvements include:

• Advanced multi-module RTL analysis.
• Larger and more diverse Verilog/SystemVerilog benchmark suites.
• Improved repair strategies for complex sequential and combinational logic.
• Automated testbench generation.
• Formal equivalence checking to strengthen confidence in behavior preservation.
• Synthesis-aware RTL optimization.
• Deeper integration with additional EDA tools.
• Exploration of NVIDIA open-source AI models and Nebius infrastructure for AI-assisted RTL engineering. These AI-model and infrastructure integrations are planned future improvements, not currently completed features.

Our long-term vision is to make hardware design, debugging, and verification more efficient through autonomous, tool-driven engineering workflows. Conclusion SiliconPilot represents a step toward autonomous hardware engineering. It does more than identify RTL problems: it analyzes designs, applies targeted repairs, and evaluates the results using real verification tools.

By combining diagnostic analysis, automated repair, iterative linting, and functional simulation, SiliconPilot aims to make RTL development more systematic, efficient, and reliable.

Our vision: From RTL Errors to Verified Designs.

Built With

• agents
• ai
• eda
• icarus
• python
• rtl
• semiconductor
• streamlit
• systemverilog
• verilator
• verilog