SiliconBreak X

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  The agent flags a suspected weakness, cites the exact RTL lines, and explains the exploit.

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  Trusted tests and a formal proof decide: the original fails, the patch passes every check.

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  Describe a circuit in plain English and the design agent engineers it end to end.

Inspiration

Software developers have AI agents that can detect vulnerabilities, fix bugs, and test their code automatically, but hardware security is a different challenge. A small mistake in Verilog can expose protected information or create security vulnerabilities directly inside a chip. Although semiconductor companies already use sophisticated verification tools, investigating vulnerabilities, repairing RTL, and proving that the repair works still requires specialized expertise. We wanted to bring autonomous AI security engineering to hardware, allowing developers to go from vulnerable chip designs to independently verified repairs with minimal manual intervention.

What it does

SiliconBreak X is an autonomous AI hardware-security engineer that detects, reproduces, repairs, and verifies vulnerabilities in Verilog designs. Bitdeer and Claude investigate hardware code for security weaknesses, while an independent verification system uses simulation and formal methods to reproduce suspected vulnerabilities. Factory Droid then autonomously modifies the RTL to repair the problem, and the verifier checks that the patch fixes the vulnerability without breaking legitimate functionality. We also built SiliconBench to compare AI security agents across different vulnerability scenarios, and an FPGA Lab that demonstrates vulnerable and repaired designs on a real Digilent Basys 3. Our flagship demonstration involved an authorization bypass that exposed a protected register through debug mode. SiliconBreak X discovered the flaw, repaired it, passed 12/12 verification tests and formal checks, and demonstrated the corrected behavior on the physical FPGA.

How we built it

We built the backend using Python and FastAPI to coordinate AI investigations, security tests, autonomous repairs, and hardware builds. Bitdeer AI Model Studio and Anthropic Claude analyze RTL security, while Factory Droid acts as the autonomous engineering agent that modifies vulnerable Verilog. Verilator handles independent hardware simulation and security testing, and Yosys provides formal verification of security properties. We created a React, TypeScript, Vite, and Tailwind frontend containing Security Lab, SiliconBench, FPGA Lab, and a natural-language hardware-development workspace. Vivado 2023.2 generates FPGA bitstreams through an isolated Docker environment running on our Apple Silicon MacBook, while openFPGALoader programs the Basys 3 after user approval. We also integrated interactive board visualizations, guided switch and button testing, and webcam-verification functionality.

Challenges we ran into

One of our biggest challenges was connecting AI-generated hardware repairs to real engineering verification. An AI can generate a convincing patch, but that doesn't guarantee the vulnerability is fixed or that the hardware still functions correctly. We had to separate the repair agent from the trusted verification system and validate both security and functional behavior. Running Vivado's x86-64 toolchain on Apple Silicon also required Docker isolation, memory management, and careful configuration to protect an existing university development environment. We encountered issues with AI API integrations, structured-output limits, FPGA programming, USB connectivity, and camera calibration. Translating a security failure from Verilog simulation into something observable through physical FPGA switches and LEDs was another major challenge.

Accomplishments that we're proud of

Our biggest accomplishment was completing an autonomous AI-to-FPGA security repair workflow during the hackathon. Bitdeer identified an intentionally introduced debug-access vulnerability, independent verification reproduced the unauthorized disclosure of a protected test value, and Factory Droid generated a working Verilog patch. The repaired design passed all 12 trusted security and functional tests along with the recorded formal proof. We successfully synthesized the agent-generated RTL, programmed it onto a real Basys 3 FPGA, and observed the unauthorized access being denied while legitimate authorized reads continued working. We also developed SiliconBench to evaluate security investigation and repair approaches using shared verification tests rather than relying on AI-generated claims alone.

What we learned

We learned that the hardest part of autonomous hardware security isn't generating code or identifying suspicious patterns, but proving that a vulnerability exists and that a repair genuinely solves it. AI-generated explanations cannot replace simulation, formal verification, and functional regression testing. We also learned how different hardware engineering is from ordinary software development, especially when dealing with Verilog, synthesis, timing constraints, FPGA programming, and physical inputs and outputs. Most importantly, we learned that combining AI agents with independent verification tools can turn model-generated suggestions into reproducible engineering results. Testing against real hardware also showed us why successful simulation alone is not enough.

What's next for SiliconBreak X

Our next goal is to expand SiliconBreak X beyond controlled demonstration circuits and evaluate it against independently sourced vulnerabilities from real open-source hardware projects. We want to strengthen SiliconBench with larger reproducible evaluations, historical security cases, secure negative controls, and comparisons of different AI investigation and repair strategies. We also plan to improve our formal verification safeguards, GitHub integration, camera-based physical testing, and support for more complex RTL designs and FPGA platforms. Ultimately, we want SiliconBreak X to become an accessible autonomous hardware-security platform that helps developers discover vulnerabilities, generate reviewable patches, and independently verify their hardware before it reaches production.

Built With

• ai-agents
• anthropic-claude
• bitdeer-ai
• digilent-basys-3
• docker
• droid-sdk
• factory-droid
• fastapi
• formal-verification
• fpga
• github
• hardware-security
• opencv
• openfpgaloader
• python
• react
• tailwind-css
• typescript
• verilator
• verilog
• vite
• vivado
• websockets
• yosys