Silicon-Simulator

From prompt to proven silicon: GPT-5.6 architects your chip, generates the RTL, runs real testbenches, and auto-fixes its own failures — idea to FPGA-ready in the browser, no EDA toolchain required

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Inspiration

Hardware design has a brutal onboarding cost. Writing correct Verilog, standing up a simulation toolchain, and debugging a failing testbench are each their own multi-day skill — long before you get to the actual chip idea. We wanted to know: what if describing a circuit in plain English, or drawing it, was enough to get working, verified RTL — not just code that looks plausible, but code that has actually passed a real simulator? That question became Silicon Canvas.

What it does

Silicon Canvas is a browser-based HDL workspace with a closed AI loop:

Describe or draw a circuit. Type a prompt ("8-bit synchronous counter with reset") or lay components out visually. A two-agent AI pipeline builds it. An Architect model reasons out a microarchitecture — modules, ports, connections, a verification plan — as strict structured JSON. An RTL Engineer model turns that spec into synthesizable Verilog and a self-checking testbench, both constrained to an Icarus-compatible subset. It actually runs. Generated RTL executes against its testbench in an isolated Icarus Verilog worker, producing real pass/fail results and a VCD waveform trace — rendered live in-browser. Auto-Fix closes the loop. If the testbench fails, one click packages the logs, VCD tail, and source into a diagnosis-and-repair pass. The fix lands as a brand-new version (originals are never overwritten) and is automatically re-simulated to confirm the repair actually works. Ship it to real hardware. A one-click export produces pin constraints and a reproducible Yosys/NextPNR build script for boards like the IceStick. Every project keeps immutable version history — you can view, diff, or restore any past version, and restoring always creates a new checkpoint rather than destroying history.

How we built it

Frontend: React 19 + TypeScript + Vite + Tailwind, with Zustand for state. Monaco powers the Verilog editor, React Flow renders the live architecture graph, and react-three-fiber drives a 3D gate-level view of the design. Backend: A deliberately dependency-light Node HTTP server (no framework) backed by PostgreSQL for versioned projects and source files. AI pipeline: Both the Architect and RTL Engineer stages call structured, schema-constrained chat completions, with a resolver that supports either Azure OpenAI or public OpenAI credentials interchangeably — the frontend never sees a key. Simulation: RTL and testbench files run inside an isolated Icarus Verilog worker so untrusted generated code never touches the main API process. Shared contracts: A dedicated packages/shared package is the only thing the frontend and backend are allowed to depend on for their API shape — an architectural rule we held ourselves to throughout, so frontend and backend work could proceed independently without breaking each other. VCD parsing: A small, dedicated vcd-core package parses waveform dumps and lays out signal changes for the Canvas-based waveform viewer.

Challenges we ran into

Getting AI-generated Verilog to actually compile. Left unconstrained, models reach for modern SystemVerilog features Icarus Verilog doesn't support well — unique/priority case, classes, randomization, inside membership tests. We had to explicitly constrain both generation and auto-fix prompts to a conservative, Icarus-safe subset, and validate every generated file server-side before accepting it. Correct overflow logic for self-checking testbenches. Naively checking finite-width signed overflow (e.g. comparing an unbounded sum to zero) produces testbenches that lie. We had to bake the correct sign-bit-based overflow formulas directly into the generation instructions so the AI's own tests were trustworthy. Keeping Auto-Fix honest. It would be easy for a repair loop to "fix" a failing test by weakening the assertion instead of the bug. We enforced — in the prompt and in review — that Auto-Fix must repair the underlying RTL or testbench logic and is never allowed to disable or soften a failing check. Isolating untrusted generated code. Running AI-generated Verilog needed real sandboxing, not just a subprocess call, so a compile-time infinite loop or resource-hungry testbench in generated code can't take down the API. Version integrity under repair. Auto-Fix and version restore both had to guarantee they never mutate history in place — every repair or restore creates a new version, so a user can always get back to exactly what they had before.

Accomplishments that we're proud of

A full generate → simulate → verify → repair loop that works end-to-end with real tool execution, not just an LLM guessing at correctness. A strict architectural boundary (shared contracts only) that let frontend and backend evolve independently without breaking each other. An Auto-Fix loop that diagnoses, patches, creates a new version, and re-verifies automatically — and is honest when the repair still doesn't pass.

What we learned

Constraining a model's output surface (schema + an explicit safe-subset of the language) does more for reliability than a cleverer prompt. And the real trust signal for AI-generated hardware isn't the code — it's whether it survives an actual simulator run.

What's next for Silicon-Simulator

Deeper waveform tooling (real zoom/pan, signal search, bus-value inspection), an interactive multi-agent copilot that explains any signal or Verilog line in plain language, and expanding the visual circuit designer so schematics and prompts feed the same generation pipeline interchangeably.

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