• 

  DE1-SoC

Simple Datapath and Controller: Scrolling Display "CPEN 311"

Overview

This project implements a simple digital datapath for a scrolling display using Quartus Prime and ModelSim (Lite Version) software. The design is loaded onto a DE1-SoC FPGA board using SystemVerilog, a Hardware Description Language (HDL).

Display Cases

Illustrations of the display cases were created prior to the circuit design to facilitate the creation of a Finite State Machine (FSM) Controller in the statemachine.sv file.

Encoding

The 7-Segment Display on the DE1-SoC is driven by active-low HEX outputs, where 0 values turn the segment ON and 1 values turn the segment OFF. The Loop Count on the LEDR outputs, however, is active-high. To accommodate this, the LEDR Driver in the driver.sv file encodes the signals as a 10-bit one-hot signal.

Circuit

Based on previous knowledge of similar digital datapaths, a top-level diagram of the circuit was created.

StateMachine

The controller of the circuit transitions through a series of states. The outputs depend on the current state, while the next state is determined by the current state, inputs, and outputs.

Datapath

The HEX0...HEX5 Displays are instantiated as modified 7-bit registers, which turn off the respective 7-Segment Display on active-high reset. The LEDR Driver is a heavily modified 10-bit register that increments a 10-bit one-hot bus as the message loops through the DE1-SoC FPGA. A Flickering Light Effect is also implemented upon completion of 10 loops around the board.

Testing

Multiple tests have been implemented to ensure the circuit functions as intended. These tests are evaluated through simulation and loading the design onto the physical DE1-SoC FPGA board.

For each of the .sv files included in this project, a corresponding testbench was written to thoroughly evaluate the functioning of the inputs and outputs. The testbenches simulate the clock and use the Verilog delay syntax to drive the clock (#). The signals are checked against expected values using the $display task.

The circuit was simulated using ModelSim, and the design was loaded onto the DE1-SoC FPGA board using Quartus Prime software.

Credit

The project was inspired by the APSC 160 - Introduction to Computation and CPEN 311 - Digital Systems Design courses at The University of British Columbia Electrical and Computer Engineering Undergraduate program. The initial idea for a scrolling 'HELLO' display was derived from APSC 160, and it was redesigned using digital design concepts from a Baccarat engine created in CPEN 311.

The project has been refactored to improve the StateMachine and testbench. The complete design document is included in the design.pdf file.

For a demonstration of our project, please watch the video here.

Built With

• systemverilog
• tcl