Saffron

Inspiration

Designing hardware is hard. Even a simple digital circuit can take time: writing Verilog, creating a testbench, running synthesis, checking simulation, reading waveforms, fixing errors, and repeating the process.

As undergraduate electrical engineering students, we saw how much time gets spent on setup and iteration before we can focus on the actual circuit idea.

Software developers have tools like Cursor to move from idea to working code faster. We wanted a similar experience for hardware: an assistant for Verilog, synthesis, simulation, and waveform-based debugging.

That is why we built Saffron - an AI-powered hardware design assistant that helps users describe a circuit, generate Verilog, verify it with real EDA tools, and visualize the result through schematics and waveforms.

Our goal is to make early-stage hardware prototyping faster, clearer, and easier to learn from.

What it does

Saffron is an AI-powered hardware design assistant for early-stage digital circuit prototyping.

Users describe a circuit in natural language, and Saffron generates Verilog for that design. The generated code is then checked using real EDA tools instead of being treated as correct by default.

If the design fails, Saffron shows the error result and can use that feedback to retry and improve the Verilog. If the design succeeds, it produces a circuit schematic and runs simulation so users can see how the circuit behaves over time.

Saffron also gives users a place to inspect and edit the generated Verilog, then rerun the workflow. This makes it useful not only for generating circuits, but also for learning, experimenting, and quickly testing design changes.

In one flow, Saffron helps users move from idea to Verilog, verification, schematic visualization, simulation, and waveform output.

How we built it

We built Saffron as a full-stack AI + EDA workflow that connects natural-language circuit design with real hardware verification tools.

On the backend, we used Python and FastAPI to create the main API. When a user describes a circuit, the backend sends the request to Claude, which generates structured Verilog code and an explanation. The generated Verilog is then passed through a verification pipeline instead of being trusted blindly.

For synthesis, we use Yosys to check whether the Verilog is valid and synthesizable. If synthesis succeeds, Yosys produces a gate-level netlist. That netlist is then rendered into a visual circuit schematic using netlistsvg and Graphviz.

For simulation, we built an automatic testbench generator. It inspects the circuit inputs and outputs, creates test cases, and runs the design using Icarus Verilog. The simulator produces a VCD waveform file, which we parse and convert into waveform data that can be shown in the frontend.

We also built an auto-repair loop. If Yosys or Icarus Verilog finds an error, Saffron captures the tool log, sends the error back to the AI with the broken Verilog, and asks it to fix the design. This loop helps turn AI output into actually working hardware code.

On the frontend, we used Next.js, React, TypeScript, and Tailwind CSS. The interface includes a chat-style circuit prompt, a Verilog editor, schematic visualization, and waveform display. Users can generate a design, inspect the code, manually edit it, and rerun synthesis or simulation.

Challenges we ran into

One challenge was connecting many different tools into one smooth workflow. AI generation, backend logic, EDA tools, frontend display, and user editing all had to work together correctly.

Another challenge was working with unfamiliar hardware toolchains under limited time. We had to learn quickly, test often, and fix issues as they appeared.

The hardest part was making Saffron feel useful instead of just impressive. We wanted the tool to help users understand and iterate on circuits, not only generate code.

Accomplishments that we're proud of

We are proud that we built Saffron in just one day while learning new EDA tools and hardware workflows along the way.

The biggest accomplishment was turning many separate pieces into one usable experience. Instead of stopping at AI-generated code, Saffron gives users a way to create, check, edit, and visually understand their circuit designs.

Even without OpenROAD integration yet, Saffron already helps users move faster in the early stages of hardware prototyping and build confidence in their designs.

What we learned

Building Saffron showed us that AI is most powerful when it is connected to real tools, not used alone.

We learned how much engineering happens between an idea and a working circuit: code generation, validation, simulation, visualization, and iteration all have to work together.

We also learned that a team does not need the same background to build something complex. Hardware knowledge, software skills, planning, and shared momentum all mattered equally.

What's next for Saffron

Saffron already works as a rapid prototyping tool for early-stage digital design. Next, we want to expand it into a more complete hardware design platform.

The next major step is integrating floor planning, layout generation, and routing, with AI helping automate and optimize each stage. Instead of only generating and verifying Verilog, Saffron could evaluate design metrics, improve layouts, and guide users toward more efficient hardware implementations.

We also want to fine-tune the AI on hardware design workflows so it becomes better at understanding circuits, fixing errors, and making stronger design decisions.

Long term, Saffron has the potential to redefine how students, engineers, and researchers build hardware by making chip design faster, more accessible, and more intelligent.

Built With

• claude-api
• fastapi
• graphviz
• icarus-verilog
• netlistsvg
• next.js
• python
• react
• svg
• tailwind-css
• typescript
• vcd-waveform-parsing
• yosys