RTL Sentinel

Inspiration

Verification consumes a substantial share of hardware engineering effort, yet requirements, tests, simulator evidence, and debugging context are often disconnected. That fragmentation creates risk: a design can appear healthy while important behavior is silently under-verified. We wanted to combine AI's ability to organize and explain engineering intent with deterministic EDA authority. In RTL Sentinel, AI can reason over bounded, validated evidence, but it never decides simulation truth and never automatically modifies RTL.

What it does

RTL Sentinel demonstrates a complete prepared-FIFO workflow:

RTL + specification → validated requirements and scenarios → deterministic SystemVerilog testbench generation → Icarus simulation → structured simulator evidence → offline or optional GPT-5.6 diagnosis → mutation campaign → final traceable report.

The validated plan contains 9 requirements and 9 scenarios with 0 uncovered requirements. Icarus Verilog and vvp are the sole simulation pass/fail authority. The generated executable testbench passes 10 checks and fails 1 at cycle 26: expected occupancy is 2, while observed occupancy is 3.

The recorded demo uses the offline analyzer. It produces an evidence-based diagnosis with confidence 0.98, rtl_modified=false, and a suggested fix direction—not a generated patch. The optional GPT-5.6 diagnosis client uses the same schema-validated boundary; no successful live GPT diagnosis is claimed.

Finally, the prepared mutation campaign attempts 4 isolated mutations: 3 are killed, 0 survive, and 1 is invalid. Therefore, 100% of valid prepared mutants are killed. This is a scoped test-strength result, not a general coverage or verification-completeness claim.

How we built it

The workflow is implemented in Python with typed Pydantic models connecting each stage. A restricted ANSI-style SystemVerilog context extractor captures the prepared FIFO interface. Jinja2 renders the deterministic self-checking SystemVerilog testbench, and a subprocess-based wrapper runs Icarus Verilog and vvp. Structured machine-readable markers are parsed into validated simulation evidence artifacts.

The offline analyzer links failures to requirements, interface context, and the specification. An optional OpenAI Responses API integration lets GPT-5.6 return the same validated diagnosis schema when explicitly enabled. API failure is handled without changing simulator truth. Mutation testing operates on isolated copies using exact-text prepared-FIFO mutation operators and classifies each result as killed, survived, or invalid. Streamlit presents the workflow, Pytest protects it with 71 passing release-candidate tests, and a shell script runs the complete offline demonstration with one command.

Codex supported repository implementation, testing, module integration, release audits, documentation, and the video package. Icarus Verilog and vvp retained final authority throughout.

Challenges we ran into

• Keeping EDA execution—not an AI response—as the source of pass/fail truth.
• Turning simulator markers into useful structured evidence without claiming full waveform inspection.
• Building a deterministic testbench that exposes the prepared simultaneous read/write occupancy defect.
• Distinguishing killed, survived, and invalid mutants relative to a baseline that already contains an intentional defect.
• Handling GPT and API failures safely through validation, timeouts, and an explicit offline path.
• Maintaining an honest two-day scope instead of implying general RTL or full SystemVerilog support.
• Keeping generated artifacts portable while acknowledging that metadata and simulator timestamps can prevent byte-for-byte equality.

Accomplishments that we're proud of

• A complete end-to-end deterministic workflow from specification to final traceable report.
• A validated plan with 9 requirements, 9 traced scenarios, and 0 uncovered requirements.
• A real prepared defect detected at cycle 26 with expected occupancy 2 and observed occupancy 3.
• Evidence-based offline diagnosis at 0.98 confidence with no RTL modification.
• A mutation campaign in which all valid prepared mutants were killed.
• 71 passing automated tests in the release candidate.
• A one-command offline shell demo and a readable Streamlit interface.
• A clean public-repository package with reproducible outcomes and a complete video asset and recording package.

What we learned

LLM reasoning is most useful when bounded by validated requirements and concrete evidence. Structured outputs are safer and easier to audit than unrestricted free-form responses. We also learned that a passing-test count says little about test strength: controlled mutation testing gives direct evidence that checks respond to relevant defects. Above all, reproducible engineering tools should retain final authority. AI can organize intent and explain evidence, while the simulator determines what actually happened.

What's next for RTL Sentinel

All of the following are future work: broader RTL support, fuller SystemVerilog parsing, waveform-aware diagnosis, multi-clock support, UVM generation, formal-verification integration, CI mutation gates, and commercial EDA adapters. These extensions would preserve the same authority boundary: validated evidence in, structured reasoning out, and deterministic tools as the source of verification truth.

Built With

• codex
• eda
• git
• github
• gpt-5.6
• hackathon
• hardware-verification
• icarus-verilog
• mutation-testing
• openai
• penai
• pydantic
• pytest
• python
• responses
• rtl
• streamlit
• systemverilog
• verilog