Radical

Modern AI inference for the places where bits flip. We created a small accelerator hardened against radiation hardening upsets, so neural nets can keep their math straight in space.

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Inspiration

NASA's Mars rovers run on the RAD750, a 200 MHz PowerPC from 2001 that costs over $200,000 per unit. It's decades behind commercial silicon, but it survives the single-event effects from cosmic radiation that would silently corrupt any consumer chip. Meanwhile, robotics and autonomy increasingly want modern neural inference. Today you can't fly that beyond low Earth orbit, because a single bit flip can corrupt your weights and your network will silently start lying to you.

One of our friends works on flight software at JPL and described it viscerally: every cosmic ray that hits the wrong transistor at the wrong moment is a coin flip on the mission. We thought: what if we built a tiny modern AI accelerator that doesn't lie to you when it gets hit?

That's Radical.

What it does

Radical is a small INT8 convolutional neural network accelerator (conv→conv→fc→fc, MNIST) implemented in SystemVerilog, with radiation hardening built around its weight memory.

The core result: SECDED Hamming ECC is integrated into the chip's live weight datapath. Every weight is stored as a 13-bit codeword (8 data + 5 parity). On read, the Hamming decoder corrects any single-bit upset before the weight reaches the MAC, and detects (flags as uncorrectable) any double-bit upset.

We prove this on the real RTL with fault injection — flipping bits directly in the chip's stored weight codewords and running inference:

  • Single-bit upset: the prediction is unchanged and the ECC correction counter increments. The chip survives the hit.
  • Double-bit upset: the prediction may change, and the double-error counter increments. SECDED can't fix a double error — but it never silently lies; it raises the alarm so the system knows the output is untrustworthy.

This is proven across three of the four weight memories (conv1, conv2, fc2), reproducible with one command (bash scripts/demo.sh).

We also built and unit-tested two further hardening blocks as standalone modules — a background memory scrubber (an FSM that walks weight memory rewriting corrected codewords so errors don't accumulate) and a triple-modular-redundancy MAC voter (triplicated multiply units with a majority vote). These are verified in isolation; wiring them into the integrated chip is our immediate next step.

How we built it

Stack: Cognichip IDE for SystemVerilog RTL and simulation, iverilog/Verilator for local sim, PyTorch for training/quantizing the MNIST CNN, Python for the host driver and fault-injection harness.

The hardening math: weights use Hamming SECDED encoding — 8 data bits + 5 parity = a 13-bit codeword that corrects any single bit flip and detects any double. The TMR voter is the classic per-bit majority circuit. These techniques are over half a century old, but they remain the workhorses of every space-rated chip ever built.

Challenges we ran into

Making the chip compile at all. Our fully-connected layer computed 25,088 multiply-accumulates in one combinational block, which made the simulator take 15+ minutes to build the chip — unworkable for iteration. We had to re-architect it into a clocked, pipelined design that processes the dot products over multiple cycles, then rework the control FSM to wait for the now-multi-cycle layer instead of assuming instant results. That dropped the full-chip compile from 15+ minutes to ~2 seconds and made integration possible.

The area/parallelism tradeoff on ECC. Protecting the small weight arrays was straightforward — one ECC codec per weight, read in parallel. But the fully-connected layer has 25,088 weights; instantiating that many parallel Hamming decoders produced a 407 MB simulation binary and is absurd in real silicon, since the layer only reads 32 weights per cycle. The correct fix is sequential per-cycle decode — a scoped change we identified but deferred. We protected the three arrays where parallel decode is feasible and documented exactly why the fourth needs a different approach.

Quantization and bias handling. Our chip currently drops the conv biases, so its predicted class differs from the full PyTorch reference — the property we prove is that ECC keeps the output unchanged under a correctable fault, not absolute classification accuracy. Reconciling full bias handling and scale factors is on the list.

Accomplishments we're proud of

  • A 4-layer INT8 CNN accelerator in SystemVerilog, every layer individually verified, with SECDED ECC integrated into the live chip datapath and proven via real fault injection — single-bit upsets corrected, double-bit upsets detected, on real RTL.
  • We got there from a chip that literally wouldn't compile by re-architecting the bottleneck layer ourselves — the genuinely hard, educational part.
  • Two reproducible RTL proofs anyone can run: a standalone ECC demo (259→247→259) and a chip-level fault-injection demo.
  • Built and verified scrubber and TMR-voter hardening modules.
  • Did this from zero chip-design experience in a weekend.

What we learned

  • Hardware-software co-design is harder than it looks — chip and host must agree on byte order, scale factors, register layout, and stream semantics; every disagreement is a debugging session.
  • AI agents are great scaffolders and questionable architects. They produce clean AXI plumbing and test harnesses, but the novel hardening logic and the real architectural decisions (pipelining the FC layer, scoping the ECC tradeoff) needed us in the loop — and when we let an agent design a voter unsupervised, the result was syntactically clean and semantically wrong. We learned to verify every block against independent hand-calculations rather than trusting any tool's self-check.
  • Modern radiation hardening doesn't have to be exotic — ECC, scrubbing, and TMR are all 1960s-era techniques.

What's next for Radical

  • Wire the scrubber and TMR modules into the integrated chip (they're built and verified standalone today).
  • Protect the FC layer's weights with the sequential per-cycle ECC decode we scoped.
  • Run the full hardened-vs-unhardened accuracy-under-fault sweep against the integrated RTL (we have a Python behavioral model of this; the RTL version is the goal).
  • FPGA bring-up for real timing/area/power numbers.
  • Open-source the hardening IP — our ECC, scrubber, and voter as a reusable SystemVerilog library.
  • Eventually, a tapeout via an open shuttle (SkyWater 130nm / eFabless) for real radiation testing.

The RAD750 is twenty-five years old. The chips that fly should move on too.

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