Pulse16_Hardware

Full-range FPGA trade signals in 243 Total Logic, with hash-bound source and repeatable verification on a Tang Nano 20K.

Comment

Team: jiexi yang
Participant: Jiexi Yang, University of Florida
Hardware: Tang Nano 20K, board 9

Project overview

Pulse16 implements the Gator Quant Hacks moving-average trading-signal specification entirely on an FPGA. It receives two item prices over UART, maintains an independent 16-price window for each item, and returns BUY, SELL, or NONE. When no crossing occurs, the previous action is retained.

The implementation supports the full unsigned 16-bit price range of 0 to 65,535, swapped item slots, and index-zero session restarts. The host computer supplies test inputs and verifies responses; signal calculations execute on the FPGA.

Implementation

The Verilog design uses a shared arithmetic datapath with 20-bit running sums. One BSRAM block stores the two price histories; a second stores per-item metadata. Compact comparison flags retain the prior price-to-average relationship needed for the next crossing decision. Stable request and response fields are reused to avoid duplicate registers within the challenge's stop-and-wait protocol.

The FPGA operates at 27 MHz. Communication uses 115200-baud UART, 8N1, without an additional programmed inter-byte response gap. Gowin V1.9.11.03 Education synthesizes and routes the design, and Gowin Programmer loads the bitstream into SRAM.

Measured results

  • Resources: 243 Total Logic, 159 registers, and two BSRAM blocks. The primitive LUT count is 206, reported separately from Total Logic; the ALU count is 36.
  • Practice qualification tests: five consecutive robust/full-range practice-test pairs passed without resetting or reprogramming, covering 1,000 complete responses and 1,680/1,680 scored actions. Warm-up responses were also checked.
  • Additional board tests: 21/21 quick-test responses, 2,000/2,000 stress-test responses, and 10,000/10,000 extended-soak responses passed.
  • Physical verification total: 13,021 checked responses, with no incorrect responses or functional-test timeouts observed in the archived sequence.
  • Round-trip latency: 16.856447 ms, the median of the five robust-test run averages.

These are local physical measurements for this exact bitstream. Round-trip latency includes the host computer and USB bridge, not only FPGA computation. The resource reduction is established; the small differences between measured host round-trip times do not establish a meaningful speed improvement.

Verification

SystemVerilog testbenches, Icarus Verilog, and independent Python checks cover full-range arithmetic, average rounding, equality boundaries, swapped item slots, and session restarts. The candidate passed RTL and mapped-circuit simulation. Additional verification passed a 133,272-packet engine replay, a 307-packet integrated UART contract audit, and a startup-equivalence check. These checks are separate from the physical-response total above.

Static timing reports no setup or hold violations at 27 MHz, with worst setup slack of +30.275 ns and hold slack of +0.199 ns. The required clock pin produces routing warning PR1014, documented in the build reports. Mapped simulation uses vendor primitive models without SDF timing annotation; physical-board tests provide separate end-to-end communication verification. Local tests do not establish an official judging score or exhaustive correctness for arbitrary traffic.

Reproducibility

Repository: https://github.com/jiexiY/gqh-pulse16

Tested release commit: e14838a7b8d194c91a62dffb61595299aba530b1

Bitstream: bitstream/trade_top.fs
SHA-256: 87400736f80c5e2d8b2bd5250f278955cfb237753736f84473c832dc8e913707

Check out the release commit and follow the README for tool setup. Run .\preflight.ps1 to validate the supplied files and hashes, load the bitstream into SRAM, and run board-test.ps1 with -Test qualification and the board's UART port. The qualification command runs the robust test followed immediately by the full-range practice test without reset or reprogramming. SRAM configuration must be reloaded after power loss.

Raw board logs and test results are included in reports/board/current243-20261004/ and reports/physical-verification.json. Resource and timing results are documented in reports/build-summary.json; the README provides additional build, simulation, and stress-test commands.

What's next

Next, I aim to make Pulse16 faster and more efficient while maintaining accurate, reliable results.

Built With

  • gowin-eda
  • icarus-verilog
  • powershell
  • pyserial
  • python
  • systemverilog
  • tang-nano-20k
  • verilog
Share this project:

Updates

Submission history