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ParetoCo : Turning Computer Architecture Design Into an Interactive Research Experiment

What if exploring a heterogeneous computer architecture did not require manually testing hundreds or thousands of CPU, accelerator, memory, scheduling, power and communication configurations?

ParetoCo is an AI-assisted computational research environment for heterogeneous computer-architecture design-space exploration.

Instead of treating architecture design as trial-and-error, ParetoCo turns it into a repeatable experiment:

Model → Constrain → Solve → Compare → Explain → Iterate

It combines a native constraint-programming engine, Synchronous Dataflow modeling, heterogeneous processor mapping, multi-objective Pareto optimization, architecture visualization, advanced system analysis, and Featherless.ai-assisted model creation and interpretation.

Most importantly:

AI does not invent the optimum. The computational engine determines feasible designs; AI helps researchers construct and understand the experiment.

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Why ParetoCo Matters

Modern heterogeneous systems can combine CPUs, GPUs, DSPs, NPUs, accelerators, memory systems and communication networks.

A researcher may need to decide:

• Which processor should execute each task?
• How many processing elements are needed?
• Which schedule satisfies the deadline?
• Does adding an accelerator actually improve throughput?
• What happens to power, area and cost?
• Does communication become the bottleneck?
• Which designs are genuinely Pareto-optimal?

The number of combinations grows rapidly.

ParetoCo turns that large search space into something researchers can model, computationally explore and visually understand.

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The Computational Core

ParetoCo's main DSE pipeline reaches a packaged native constraint-solving engine.

Architecture + SDF Workload + WCETs + Constraints
                         ↓
                Node.js Solver Bridge
                         ↓
              Native DSE / Gecode Engine
                         ↓
             Feasible System Mappings
                         ↓
                 Pareto Analysis
                         ↓
          Interactive Research Workspace

The engine explores heterogeneous resource allocation, task-to-processor mappings, schedules, communication constraints, throughput, power, timing and resource limits.

It supports multiple search strategies, presolving, configurable search parameters and multiple feasible solutions instead of returning a single arbitrary answer.

On Windows, ParetoCo launches the native executable directly. The hosted Docker deployment uses Wine to preserve the same native engine on Linux.

Native failures are exposed as failures instead of being silently replaced by fake solver results.

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From “Best Design” to a Pareto Frontier

Architecture research rarely has one perfect solution.

A faster system may consume more power. A cheaper architecture may increase latency. An accelerator may improve computation while worsening communication.

ParetoCo therefore compares designs across dimensions including:

latency · throughput · power · area · cost · utilization · processor count · memory

Its optimization stack includes:

• Pareto dominance
• fast non-dominated sorting
• crowding distance
• hypervolume
• knee-point detection
• solution clustering
• sensitivity analysis
• interactive filtering
• parallel-coordinate visualization

Instead of answering:

“Which architecture is best?”

ParetoCo helps answer:

“What does each improvement cost, and where is the most useful trade-off?”

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Architecture Studio

ParetoCo also provides a visual architecture environment containing:

CPUs · GPUs · DSPs · NPUs · accelerators · memory · buses · NoC components · workload actors

Researchers can build and modify architectures visually, connect components, inspect properties and synchronize the diagram with the underlying computational model.

Most importantly, native solver mappings can be projected back onto the architecture.

So the visualization is connected to the experiment rather than being a decorative diagram.

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More Than a DSE Solver

ParetoCo includes a broader analytical research stack for understanding why designs behave differently.

Graph & Scheduling

Tarjan SCC, cycle detection, topological sorting, Dijkstra, Floyd-Warshall, Dinic max-flow and critical-path analysis.

Streaming / SDF

Maximum Cycle Ratio, critical-cycle extraction, throughput estimation and self-timed simulation.

Network-on-Chip

2D mesh generation, XY routing, link utilization, saturation analysis and communication bottleneck detection.

Energy & Thermal

DVFS analysis, energy estimation, steady-state thermal models and transient RK4 thermal simulation.

Memory Systems

L1/L2 cache simulation, scratchpad allocation, NUMA contention, memory-pressure analysis and MESI-style coherence simulation.

Real-Time Systems

response-time analysis, deadline checking, blocking analysis and schedulability reasoning.

Reliability

failure-rate analysis, redundancy/backup synthesis and reliability/MTTF estimation.

Optimization & Diagnostics

SPEA2-style metrics, Simplex optimization, constraint slack analysis and QuickXplain-style infeasibility diagnosis.

This lets ParetoCo investigate architecture as a system, rather than optimizing processor speed while ignoring everything around it.

---

Featherless.ai as a Research Assistant

ParetoCo's strongest AI workflow is Natural Language → DSE Model.

A researcher can describe a requirement such as:

“Use four CPUs and two NPUs, keep latency below 30 ms and prioritize energy efficiency.”

The Featherless tool-calling pipeline can convert that into structured:

• hardware/platform definitions
• applications
• WCET information
• constraints
• DSE settings

If important information is missing, it can ask for clarification before completing the model.

After exploration, actual solution metrics can also be given back to the AI layer for easier interpretation.

So the workflow becomes:

human idea → AI-assisted model construction → computational exploration → AI-assisted explanation

rather than:

prompt → guessed architecture

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Designed for Iterative Research

Research rarely stops after one solver run.

ParetoCo therefore tracks:

• experiment sessions
• model snapshots
• run history
• semantic changes
• constraint changes
• solution changes
• Pareto-front evolution
• invalidation impact
• warm-start seed candidates
• exploration branches

This makes it possible to ask:

What changed between two experiments?

Which requirement removed these solutions?

How did adding another accelerator move the Pareto frontier?

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Why We Built It

ParetoCo was built by a four-person team:

Muhammad Taha Bin Zaeem, Alizay Hasan, Lameea Mubashir Khan, and Idrees Babar.

As Computer Engineering students, we were interested in architecture research, but we saw a major gap between learning about processors, scheduling, dataflow, memory systems, optimization, and heterogeneous computing and actually being able to experiment with all of them together.

ParetoCo grew from a simple question:

“How can we turn an architecture idea into a computational experiment instead of only reasoning about it theoretically?”

We wanted to explore questions such as:

• When does adding an accelerator stop improving performance?
• How much power must be traded for lower latency?
• When does communication become the real bottleneck?
• Which mappings remain Pareto-optimal when constraints change?
• Why does a previously feasible architecture suddenly become impossible?

ParetoCo became our way of turning those questions into repeatable, visual, computational research experiments—and of making advanced computer-architecture exploration more accessible to students and researchers.

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Building on Existing DSE Research

ParetoCo stands on a long research lineage.

Systems such as Sesame explored heterogeneous MP-SoC design spaces; IDeSyDe formalized modular design-space identification; FARSI explored domain-specific SoCs; and later work has investigated heterogeneous accelerators and end-to-end latency-aware DSE.

ParetoCo does not claim to replace these mature research frameworks.

Its contribution is bringing many parts of the workflow together:

visual modeling + constraint-based DSE + Pareto analysis + architecture analysis + experiment tracking + AI-assisted interaction

inside one accessible environment.

A workflow that might otherwise involve multiple independent modeling, optimization, visualization and analysis tools can be explored from one interface.

---

What This Could Enable Next

ParetoCo creates a foundation for research into:

CPU–GPU–NPU co-design, communication-aware accelerator mapping, thermal-aware DSE, memory-aware mapping, reliability-aware optimization, explainable infeasibility, and human–AI collaboration in architecture research.

One especially interesting future question is:

Can an AI assistant reduce the difficulty of formulating computer-architecture experiments while a deterministic solver preserves mathematical trust?

Our next major step is therefore not adding more isolated features.

It is closing the loop:

AI proposes → native solver verifies → ParetoCo analyzes → AI interprets → researcher decides.

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What We Are Proud Of

ParetoCo is not just a visualization, an LLM wrapper, or an optimization script.

It connects modeling, native computation, multi-objective analysis and human interpretation into one research workflow.

And for me, as a second-year Computer Engineering student, the biggest accomplishment is simple:

I can now take “what if?” questions about computer architecture and turn them into computational experiments.

Built With

• ai-research
• architecture-modeling
• computational-research
• computer-architecture
• constraint-programming
• design-space-exploration
• dvfs
• embedded-systems
• featherless-ai
• gecode
• hardware-software
• heterogeneous-computing
• memory-systems
• multi-objective-optimization
• noc-analysis
• pareto-optimization
• paretoco
• performance-optimization
• real-time-systems
• reliability-analysis
• research-tools
• schedulability
• synchronous-dataflow
• system-design
• thermal-analysis