PACI: Physics-Informed Anomaly Classification for TinyML

💡 About the Project

Continuous machine learning inference on edge sensors in industrial environments—such as semiconductor plasma etch chambers, turbine vibration monitors, and motor telemetry—faces severe energy, memory, and thermal constraints. Standard TinyML systems run deep neural networks 100% of the time, burning precious milliwatts classifying normal, benign steady-state operation. Conversely, simple moving-average statistical baselines normalize away slow physical equipment drift, missing up to 25% of critical faults.

PACI (Physics-Informed Anomaly Classification for TinyML) solves this fundamental edge AI dilemma using an evidence-proportional, 3-tier adaptive cascade designed for Arm Cortex-M microcontrollers:

  1. Tier 0 — Physics-Informed EKF State Predictor ($\sim 465\text{ ns}$ execution latency, $0\text{ B}$ scratch RAM):
    An analytical Deal-Grove physics model coupled with a scalar Extended Kalman Filter and Normalized Innovation Squared ($\text{NIS}$) statistical gating: $$\text{NIS}t = \frac{\nu_t^2}{S_t} = \frac{(z_t - \hat{z}_t)^2}{H P{t|t-1} H^T + R} \le \chi_{1, 0.95}^2 = 3.841$$ During nominal operation ($\text{NIS}_t \le 3.841$), neural networks remain completely asleep, filtering out 84.85% of nominal cycles while maintaining sensitivity to real physical drift.

  2. Tier 1 — INT4 1D-CNN Anomaly Screener ($22.42\text{ }\mu\text{s}$ latency, $216\text{ B}$ weights):
    An ultra-compact 4-bit convolutional screener using CMSIS-NN arm_convolve_s4 with packed nibbles ($2\text{ weights/byte}$) that resolves 70.30% of escalated anomalies in less than a quarter of the time of a full classifier.

  3. Tier 2 — INT8 1D-CNN Fault Classifier ($110.52\text{ }\mu\text{s}$ latency, $11.8\text{ KB}$ weights):
    A full 5-class fault classification model using CMSIS-NN arm_convolve_wrapper_s8, invoked only on confirmed anomalies or periodic watchdog audits ($4.50\%$ of cycles).

📊 Measured Benchmark Results (Canonical 2,000-Step Trace)

Evaluated across a deterministic 2,000-step process sequence (bench_trace.h) conforming strictly to Schema v3:

  • Tier 1 Invocations ($N_1$): $303\text{ / }2,000$ ($15.15\%$ escalation rate)
  • Tier 2 Invocations ($N_2$): $90\text{ / }2,000$ ($4.50\%$ escalation rate)
  • Effective Realized Latency: $11,510.15\text{ ns/step}$ (vs $122,209.20\text{ ns/step}$ Always-On baseline)
  • End-to-End Compute Reduction: $90.58\%$
  • Effective Acceleration Speedup: $10.62\times$
  • Classification Parity: $100\%$ match against the unquantized reference model on the validated test set.

🌟 Inspiration

Embedded developers are often forced into an uncompromising trade-off: either deploy an inaccurate heuristic filter to save battery life, or deploy an always-on neural network that exhausts the micro-energy budget and overheats the enclosure.

We realized that in physical cyber-physical systems, the underlying physics is already known. Rather than discarding domain equations and relying solely on data-driven neural nets, we can use lightweight first-principles physics models (Deal-Grove oxidation/etch kinetics) as real-time statistical guards. Physics handles the 90%+ nominal baseline for nanoseconds of compute; neural networks are reserved strictly for anomalous physical deviations.


🛠️ How We Built It

  1. Embedded Production C Core (paci_core/):

    • Implemented a zero-heap, deterministic C library containing Deal-Grove physics (paci_physics.c), scalar EKF with covariance health protection (paci_ekf.c), bounded linearizing circular buffers (paci_ring.c), and tri-tier cascade dispatch (paci_cascade.c).
    • Sized for microcontrollers: runs in an isolated $8,192\text{ B}$ static scratch arena with zero dynamic heap allocations.
  2. Quantization & CMSIS-NN Optimization:

    • Developed custom post-training quantization tools (tools/export_cmsisnn.py) extracting weights and quantizer scales directly into CMSIS-NN C headers.
    • Vectorized for Arm Cortex-M55 / Helium MVE using CMSIS-NN v7.0.0 and CMSIS-DSP v1.17.1.
  3. Mathematical Single-Rounding Bias Proof (docs/BIAS_BUDGET.md):

    • Analyzed CMSIS-NN arm_nn_requantize round-half-up mode (CMSIS_NN_USE_SINGLE_ROUNDING).
    • Derived the cumulative rounding bias bound across chained convolution, pooling, and dense layers: $$|\epsilon_{\text{total}}| \le 1.25\text{ LSBs}$$
    • Proved mathematically and empirically that because the minimum classification margin is $\ge 4.0\text{ LSBs}$, zero class-label flips occur due to integer rounding error.
  4. Automated Testing, Benchmarking & CI:

    • Engineered standalone C measurement harness (bench/bench_main.c) supporting hot/cold cache thrashing differencing.
    • Created cross-compilation and profiling infrastructure for the Arm Corstone-300 FVP (bench/fvp_profile.py).
    • Automated full test suite ($96\text{ / }96$ passing tests) and Schema v3 benchmark reporting in GitHub Actions targeting ubuntu-24.04-arm runners.

🧗 Challenges We Faced

  • Reconciling INT4 Dense Layers with CMSIS-NN: CMSIS-NN's arm_fully_connected_s4 kernel requires per-tensor quantization parameters, whereas standard TFLite export produces per-channel scales. We engineered an exact float-rescaling transformation in our exporter to collapse channel ranges into a unified, overflow-safe INT4 scale without precision loss.
  • Ring Buffer Linearization for Sliding CNN Windows: Passing circular buffer slices directly to 1D-CNN kernels caused memory segmentation faults across pointer wrap boundaries. We built paci_ring_read() to perform zero-copy chronological linearization into a fixed contiguous buffer.
  • Honest Baseline Comparison: Original benchmarks tested extreme $125\sigma$ faults where even trivial heuristics succeeded. We implemented a realistic fault difficulty ladder (0.5$\sigma$ to 2$\sigma$ drift), proving that Moving Average misses $25\%$ of slow equipment drift while PACI's physics model achieves $100\%$ detection.

🎓 What We Learned

  • Physics and TinyML are complementary, not competing: A scalar physics equation executing in just $465\text{ ns}$ can shield neural inference for over $84\%$ of operating time while retaining true physical sensitivity.
  • Aggressive INT4 Quantization is production-ready on Arm: Pairing 4-bit weights with a cascade architecture delivers $216\text{ B}$ memory footprints without compromising system-level classification accuracy.

Built With

  • aarch64
  • arm-cortex-m55
  • c
  • cmake
  • cmsis-dsp
  • cmsis-nn
  • corstone-300-fvp
  • edge-ai
  • embedded-systems
  • github-actions
  • helium-mve
  • kalman-filter
  • linux
  • matplotlib
  • numpy
  • physics-informed-ml
  • pytest
  • python
  • semiconductor
  • tensorflow-lite
  • tinyml
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