LLM Enabled Chip Verification Using XCompaction Method

Large Language Models are curated self attention heads running across matmul operations in solving chip defects in the chip.

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Inspiration

The constructive interface for High Bandwidth Memory via chip interconnect acts in accordance to functional blocks which is a constraint in analog IC whereas it is an advantage in case of unsupervised tasks in particular to address the bias voltage via si interconnects. Inorder to decipher the hardware instructions which is primarily time consuming when scaling the electronic devices to theoretical minimum. So, It inspired me to understand adverse guardrails pertaining to segmentation tasks in semiconductor physics and trim irrelevant verification scheme through XCompaction Technique

What it does

The Schema for LLM training is done through transformer architecture and evaluate the matmul operations in verilog.c/test.cpp with supporting benchmarks like BELU score, cross_eval, context_window etc. The Cyclical paradigm for > 4nm chips is done in seven iterations until computational irreducibility is achieved through XCompaction only on RTL Synthesis.

How we built it

We built it with the following checkpoints in mind they are:

1) ** Expert-Oriented Training and Fine-Tuning ** : Constructing such frameworks heavily relies on expert efforts for training or fine tuning them to accommodate specific ASIC flows. Given the variety of technologies with their respective documentation, syntaxes, flows, and scripting methods, the pre-trained LLM may not offer a universally applicable model for all environments.

(2) *Failure in Handling Unforeseen Incidents * : Despite extensive finetuning, the LLM-based agent may inaccurately extract information from reports/specs or generate incorrect scripts/configs when confronted with new incidents in the flows. Technology advancements, EDA tools updates, etc., may worsen this issue, as the LLM agent may fail to provide the desired output under evolving conditions.

Let's look into code example based on system, user prompt dialogue box

** system ** always @(posedge clk) begin if (rst) begin internal_data <= {WIDTH{1'b0}}; end else if (scan_enable) begin internal_data <= {internal_data[WIDTH-2:0], scan_in}; end else begin internal_data <= data_in; end end

** user ** module shift_register #( parameter WIDTH = 8) ( input wire clk, // Clock input input wire rst, // Reset input input wire enable, // Enable input for data_in input wire [WIDTH-1:0] data_in, // Data input output wire [WIDTH-1:0] data_out, // Data output input wire scan_enable, // Enable input for scan_in input wire scan_in, // Input for scan output wire scan_out // Output for scan ); reg [WIDTH-1:0] internal_data; // Internal shift register data // Shift register operation always @(posedge clk) begin if (rst) begin // Reset: Fill shift register with zeros internal_data <= {WIDTH{1'b0}}; end else begin // Regular operation if (scan_enable) begin // Shift in scan_in if scan_enable is asserted internal_data <= (WIDTH > 1) ? {internal_data[WIDTH-2:0], scan_in} : {1'b0, scan_in}; end else if (enable) begin // Shift in data_in if enable is asserted internal_data <= (WIDTH > 1) ? data_in : {1'b0, data_in}; end end end

Challenges we ran into

We have faced negative current density in IC circuits above threshold limit but we have addressed it with wafer bonding technique between high K dielectrics & 80 micro meter SiN3 layer to address thermal conductivity of compact devices like photonic devices

Accomplishments that we're proud of

  1. We have accomplished Net Fault Tolerant Network (FTN) during model training & metal wiring in physical circuits.
  2. Surface Bumps & Crystallographic properties are altered during the course of chip interconnect where we employed ** LLMs ** to address the bottleneck.

What we learned

  1. Dive into unreal problem solving ability during interface building process
  2. Focus on Reinforcement Learning through Human Feedback (RLHF) and apply during LLM Research

What's next for LLM Enabled Chip Verification Using XCompaction Method

** Built Max Hallucination free LLM Model (Entropy State) during heavy computational tasks leading to Fault Tolerant Boltzmann Machines (FTBM) **

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