LC-3

This project involves building a functional computer, which will be able to run simple programs. The computer I will be building will be a modication of the LC-3 (the LC-M), which supports the following instructions: ADD, AND, BR, LDR, LEA, NOT, STR, and HALT. I will be creating various components: ALU, CC-Logic, PC, ADDR, and SRC2MUX.

1. Program Counter (PC) The PC is a 16-bit register that holds the address of the next instruction to be executed. During the FETCH stage, the contents of the PC are loaded into the memory address register (MAR), and the PC is updated with the address of the next instruction. There are two scenarios for updating the PC:
2. The contents of the PC are incremented by 1.

3. The result of the ADDR is the address of the next instruction. The output from the ADDR should be stored in the PC. This occurs if we use the branching instruction, (BR).

4. Instruction Register (IR) The IR is a 16-bit register that holds the machine code of the current instruction. During the FETCH stage, the LC-M interrogates memory for the instruction, which gets loaded into the memory data register (MDR). Then, the contents of the MDR are loaded into the IR. The contents of the IR are then decoded and executed. There are two LC-M instructions that use constants: ADD and AND. For example, ADD R0, R1, 2 adds the constant 2 to the contents of register 1 and stores the result in register 0. This constant is called imm5 (immediate 5) and is stored in the 5 least signicant bits of the instruction. These 5 bits are sign-extended to 16 bits so that imm5 can be used in other components of the LC-M.

5. ADDR The ADDR is used to calculate addresses during the following instructions: BR | 0000 | nzp | PCoffset9 | LDR | 0110 | DR | baseR | offset6 | LEA | 1110 | DR | PCoffset9 | STR | 0111 | SR | baseR | offset6 |

Built With

• assembly