Verity: AI Hardware Engineer

Inspiration In September 2026, OpenAI and Synopsys announced GPT-Synopsys: a model built to run Synopsys's chip design tools, with agents that run the tools, read the results, make changes and work toward verified designs. It is a closed model on commercial tools, and it is still at the early customer stage.

That made us ask: can open models do this today, with open-source tools? How would NVIDIA Nemotron and GLM do if the model writes the design and code decides what passes? The checking is the hard part: RealBench found that 44.2% of GPT-4 Turbo's Verilog that passed its tests still failed a formal check. And since NVIDIA is a chip company itself, building a chip engineer on Nemotron felt like the right fit.

What it does Verity is an agentic chip engineer. You describe a chip, and it: Checks the request against live web sources (Tavily) and says if it can build it. Writes the Verilog with NVIDIA Nemotron. Tests it against a locked golden model the agent cannot see or change. Fixes its own bugs from the failing cases, then runs again. Optimizes it for your goal (smaller, faster or lower power), with every number measured by open EDA tools and a formal check against version one. From one request it built a whole RISC-V CPU: 7 of 7 blocks passed, the core ran 18 of 18 programs and passed 44 of 44 riscv-formal checks, for $1.09 in model calls. A 2-stage pipeline upgrade then ran the same benchmarks in a third of the time.

How we built it Models on Nebius Token Factory: Nemotron 3 Ultra plans, writes and repairs the Verilog; Nemotron 3 Super tries the smaller and faster versions; Nemotron 3.5 Lightning routes chat messages; GLM 5.3 runs the chat and summarises research. Nemotron writes every line of Verilog. Backend: Python and FastAPI with a fixed state machine. The model never runs a tool. Tools: Icarus Verilog with cocotb, Verilator, Yosys, OpenSTA, Yosys EQY and riscv-formal, in a Docker sandbox. Frontend: Next.js and React, with Supabase for accounts.

Challenges we ran into Compute for bigger chips. Every block goes through lint, simulation, synthesis, timing and formal checks, many times over, while the agent repairs and optimizes it. One small RISC-V CPU took about 33 minutes. We did not have the compute for a big pass on a large chip, so we limited Verity to an RV32I RISC-V CPU and four small chip families, with spend caps on every run. Picking the right model for each job. We tested GLM 5.3, Nemotron 3 Ultra and DeepSeek on the same 24 chat messages. Some models offered designs Verity cannot build, so GLM got the chat and Nemotron kept the engineering. Reasoning tokens. Nemotron's thinking counts against the output limit and cut early plans off, so we measured every call and set the limits from real data. Formal checks are strict. riscv-formal even found a gap in our own CPU rules. We fixed our rules instead of weakening the check.

What we learned How chips are really built. None of us started as hardware engineers, so we had to research a lot: how a design goes from a spec to RTL, how it is simulated against a reference model, synthesized into gates, timed, and formally checked, and how a RISC-V CPU is split into blocks and verified instruction by instruction. We learned the open tools engineers use for each step (Icarus Verilog, cocotb, Yosys, OpenSTA, Yosys EQY, riscv-formal) and why verification takes most of the work. Let the model write, and let code judge. Locked tests, real measurements and formal checks made the agent trustworthy in a way better prompts never did. The right model for each role beats the biggest model everywhere.

What's next Bigger chips. With more compute, Verity can run larger designs and longer improvement passes, beyond a small RISC-V CPU. A design workspace for engineers. A proper design UI where the engineer and the agent architect the chip together: sketch the blocks, discuss the trade-offs, and let the agent build and check each part, an agentic conversation with the engineer instead of one request. More chip families (an FP8 multiplier, a FIFO, CRC-32), custom blocks you approve yourself, and full runs on the hosted site through Nebius Sandboxes. Sources for the inspiration: OpenAI and Synopsys, "OpenAI and Synopsys Announce GPT-Synopsys", 2026-09-30 (investor.synopsys.com); RealBench, arXiv 2507.16200.

Built With

• cocotb
• docker
• fastapi
• glm
• icarus-verilog
• nebius-token-factory
• next.js
• nvidia-nemotron
• opensta
• pydantic
• python
• react
• risc-v
• riscv-formal
• serper
• sqlite
• supabase
• tavily
• typescript
• vercel
• verilator
• verilog
• yosys
• yosys-eqy