GQH_Hardware_Stark-Silicon

Inspiration

We were driven by the core challenge of the Gator Quant Hacks Hardware Track: putting a trading strategy directly into silicon. The competition's 100-point rubric heavily rewards hardware efficiency, dedicating 15 points to minimizing the total LUT count against a 542-LUT reference design. Instead of settling for a standard textbook architecture, we were inspired to aggressively optimize our Verilog design and exploit FPGA-specific features to push the Tang Nano 20K to its absolute limits.

What it does

The Silicon Trade Core acts as a hardware-accelerated trading algorithm. It receives 8-byte price packets from the judge's PC over a 115,200 baud serial link. For each packet, it routes the incoming prices to independent state engines based exclusively on their item IDs (0x11 for Item A, 0x22 for Item B). It updates a 16-sample moving average for each item, performing floor division by 16 to calculate the new average. It then evaluates if the price crossed the average to trigger a BUY or SELL action, and echoes an 8-byte response back to the PC mirroring the exact slot order of the request.

How we built it

We built the architecture from scratch in Verilog using Gowin EDA. To minimize our LUT footprint, we threw out traditional data buffers. Our UART receiver steers incoming bits directly into target registers on the fly, and our parser identifies items using just a single bit rather than synthesizing 8-bit comparators. To handle the moving average math, we mapped the 32 historical prices to the FPGA's True Dual-Port BSRAM, keeping them completely out of the LUT count. We also replaced wide 16-bit comparators with boolean crossing logic to evaluate the BUY and SELL conditions.

Challenges we ran into

Our biggest hurdle was the Tang Nano 20K's onboard BL616 USB-serial bridge. The competition guidelines warned that the BL616 drops or corrupts bytes if response bytes are sent back-to-back with no idle time, which triggers a run-ending timeout. We had to inject idle time between our transmitted bytes to prevent this. However, the judge's latency measurement includes any delay we add, and we needed to stay under approximately 20.8 ms to earn full latency points. Balancing this trade-off between reliability and speed required precise bit-time tuning in our UART transmitter's state machine.

Accomplishments that we're proud of

We are incredibly proud of our objective hardware efficiency. By utilizing shiftless UART routing and BSRAM inference, we drastically undercut the 542-LUT reference design. Furthermore, we successfully engineered a zero-buffer architecture that asserts its packet-done flag during the middle of the incoming 8th byte's stop bit. This allows our state machine to safely begin driving the outgoing start bit microseconds later, squeezing out absolute minimum latency while remaining fully compliant with the protocol requirement to receive all 8 bytes before responding.

What we learned

We learned how much PC and USB overhead dominates real-world hardware communication. Even though our FPGA processes a packet in fractions of a millisecond, the reference round-trip latency measured on the judge's PC is around 16.6 ms. We learned that this delay is heavily dominated by the BL616 bridge, USB polling rates, and operating-system serial buffering. This taught us to focus our optimizations on architectural efficiency and LUT reduction rather than chasing nanoseconds in the datapath.

Full final commit SHA: 3aae6a2aaa6de3cc07e245c7df38c03dbf0b19c1

Built With

• gowin
• python
• verilog