Frembed

About the Project

Inspiration

Learning HDL and FPGA design has a steep curve that is very different from software development. While platforms like LeetCode exist for programming, there is no equivalent environment that helps learners practice hardware thinking such as understanding parallelism, timing, memory bandwidth, and resource constraints. Most FPGA tools focus on synthesis and implementation, but they do not explain why a design behaves the way it does or how to improve its architecture.

Frembed was inspired by this gap. The goal was to create a platform that helps learners move from writing functionally correct HDL to designing efficient and timing aware hardware that maps well onto real FPGA devices.

What I Learned

Building Frembed reinforced how fundamentally different hardware design is from software. Concepts such as spatial parallelism, pipelining, and clock domain isolation are not optional optimizations. They define correctness and performance.

I also learned the importance of deterministic analysis in HDL tooling. Many hardware issues such as inferred latches, unsafe clock crossings, or long combinational paths are structural problems that benefit from rule based detection and clear visualization rather than probabilistic approaches.

From a systems perspective, the project highlighted the challenges of safely executing and analyzing untrusted HDL code, managing simulation artifacts, and presenting complex hardware behavior in a way that is approachable for learners.

How the Project Was Built

Frembed is built as a full stack platform with two main workflows.

1. LeetCode style HDL practice
   Users solve structured VHDL and Verilog problems designed around common FPGA design patterns such as counters, finite state machines, pipelines, and memory interfaces.

2. File based design analysis
   Users can upload existing HDL designs. The system performs static and dynamic analysis to evaluate structure, timing boundaries, and architectural efficiency.

Simulation is handled using open source tools such as Icarus Verilog and GHDL. Designs are validated using hidden testbenches, and waveform data is captured using VCD files for inspection. Heuristic analysis is applied to identify opportunities for improvement, including the following.

Data parallelism and spatial replication
Loop unrolling and loop pipelining with target initiation intervals such as
[ II = 1 ]
Memory partitioning and banking for higher bandwidth
Pipelining to reduce critical path delay and improve
[ f_{MAX} ]
Safe clock domain crossings using FIFOs
Resource sharing and fixed point arithmetic for area efficiency

The frontend presents these results through a clean interface that emphasizes signal behavior, timing, and hardware structure rather than compiler style error messages.

Challenges Faced

One of the biggest challenges was balancing depth with clarity. FPGA design concepts can become overwhelming quickly, especially for learners. Presenting meaningful feedback without oversimplifying required careful abstraction and prioritization.

Another challenge was safely handling untrusted HDL code. Simulation requires executing user submitted designs, which introduces security concerns. The MVP uses a constrained execution model, with plans for stronger isolation using container sandboxing in future iterations.

Finally, translating low level hardware behavior into actionable insights required careful reasoning about what can be inferred reliably without full synthesis and place and route. Frembed intentionally avoids claiming exact resource counts or timing slack, focusing instead on structural and architectural guidance.

Looking Forward

Frembed aims to grow into a practical learning and analysis tool that helps bridge the gap between writing HDL and designing efficient FPGA hardware. Future work includes deeper architectural analysis, expanded challenge libraries, and tighter integration with board specific constraints.

The long term vision is to make hardware design more approachable by giving learners fast feedback and a clear mental model of how their HDL maps to real hardware.

Built With

• docker
• docker-compose
• fastapi
• ghdl
• google-gemini-api
• icarus-verilog
• javascript
• python
• react
• sqlite
• typescript
• verilog
• vhdl
• vite