Fractal_Generator

Author: IrrelevantOnGit

Project Overview

This project implements a high-performance Mandelbrot set generator using pure Verilog RTL. It eliminates the need for a NIOS processor by deploying an array of parallel calculation engines. These engines compute the Mandelbrot set for specific x,y coordinates and populate a VGA frame buffer. The entire system, including VGA timing generation and memory management, is synthesized on an Altera EP4CE115 FPGA.

Theory of Operation

The Mandelbrot set is defined in the complex plane. The core task is to determine if the iterative function $C$ converges or diverges for a given point.

The function is defined as: $$ C_{n+1} = C_{n}^2 + C_{0} $$

Where the initial condition $C_{0}$ represents the coordinates $x + iy$ in the complex plane.

If the magnitude of $C$ stays within a threshold after a fixed number of iterations, the point is considered convergent (part of the set) and is plotted on the display.

FPGA Implementation Details

The design targets the Altera EP4CE115F29C7 FPGA (DE2-115 kit) and generates a 640x480 VGA video output.

Key Components

Calculation Engines: The system supports a pool of up to 12 engines (tested). Each engine utilizes a state machine performing Q8.24 fixed-point arithmetic, requiring 4 clock cycles per iteration.
coor_gen.v: This module acts as a dispatcher, generating coordinate pairs and assigning them to idle engines.
Engine2VGA.v: This unit manages the write-back process. It takes results from completed engines and updates the correct address in the VGA frame buffer (implemented via internal dual-port RAM).
VGA.v & VGA_controller.v: These modules handle the display interface. They read from the frame buffer, apply color mapping via a look-up table, and generate the necessary sync signals for the monitor.

Performance

The architecture allows for scalable performance. As more engines are added, the frame rate improves linearly. The engines run in a separate clock domain (managed by engine_pll.v), allowing independent frequency tuning.

Benchmarks (Engines running at 112 MHz):

4 engines: 5.04 fps
8 engines: 9.37 fps
12 engines: 20.5 fps

Contrast: A pure NIOS II soft-core processor at 50 MHz takes over 12 minutes to render a single frame.

Areas for Improvement

Algorithm Efficiency: Reducing the multiplication count in the core algorithm could yield faster processing times.
Resource Optimization: The engines currently use 9-bit embedded multiplier blocks (20 blocks per engine). With 12 engines, 93% of the FPGA's multipliers are consumed. Reducing this usage would allow for more parallel engines.
Zoom Feature: Implementing hardware controls (using DE2-115 buttons) to zoom into the fractal.
Color Mapping: The visual output could be enhanced with better coloring algorithms. This would involve modifying the imag_index.v ROM and the pre-loaded index_logo1151.mif table.