FPGA stuff

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  The implementation of above

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  What the conv1 conv2 MP looks like on vivado

Inspiration

Since we have written a lot of Verilog codes, we decide to utilize the convenience that Vivado brought to us, the block diagram. Making some libraries regarding AI applications may be useful.

What it does

It is an easy-to-use block. Just place it in the block diagram and auto-wire, then everything should supposedly done.

How we built it

We built the block through HLS instead of hand-written since we wanted to make sure we have explored more solution space. Then, we build up a wrapper just to make it easy to use.

Challenges we ran into

Debugging HLS is actually very time-consuming.

Accomplishments that we're proud of

It may have worked?

What we learned

HLS is hard.

What's next for FPGA stuff

Making up more library stuff is possible.

Built With

• verilog