EdgeFlex AI

Inspiration

Deploying AI on small ARM Cortex-M microcontrollers is challenging because embedded devices have limited SRAM, Flash, processing capability, and power resources. We were inspired to explore whether a lightweight runtime architecture could make on-device AI execution more efficient on resource-constrained microcontrollers.

This led to EdgeFlex AI, a lightweight AI runtime framework focused on efficient memory management and modular AI execution on ARM Cortex-M devices.

What it does

EdgeFlex AI provides a modular runtime architecture consisting of:

Runtime Core
Model Loader
Dynamic Memory Manager
Inference Engine
Performance Monitor

The main innovation is the Dynamic Memory Manager. Instead of reserving memory for the entire AI model, the runtime is designed to allocate memory when required, release it after execution, and reuse the available memory for subsequent neural-network layers.

This approach aims to reduce peak SRAM usage and improve memory efficiency during on-device AI execution.

How we built it

We are developing EdgeFlex AI using Embedded C and STM32CubeIDE, with the STM32 HAL layer providing the hardware abstraction.

Our initial hardware platform is the STM32 Black Pill based on the STM32F401CCU6 ARM Cortex-M4 microcontroller.

The framework is organized into independent runtime modules so that memory management, model loading, inference, and performance monitoring can be developed and optimized separately.

Challenges we ran into

The main challenge was designing a memory-management approach suitable for a microcontroller with limited SRAM while keeping the runtime lightweight.

We also had to design the runtime architecture so that memory allocation and reuse could work without introducing unnecessary runtime overhead.

Another challenge is integrating AI model execution while maintaining the modularity and portability of the framework.

Accomplishments that we're proud of

Designed the EdgeFlex AI runtime architecture
Developed the initial Runtime Core
Designed the Dynamic Memory Manager
Created a modular runtime structure
Established the STM32 HAL integration layer
Successfully compiled the current firmware with 0 errors and 0 warnings
Created a foundation for AI model integration and benchmarking

What we learned

We learned how runtime architecture affects AI deployment on resource-constrained microcontrollers.

We gained practical experience in embedded C, STM32 development, modular firmware architecture, memory management, and ARM Cortex-M based embedded systems.

Most importantly, we learned that efficient memory management is a critical part of making AI practical on small edge devices.

What's next for EdgeFlex AI

Our next steps are:

Implement the AI Model Loader
Develop the Inference Engine
Integrate the Performance Monitor
Deploy a lightweight AI model on the STM32 Black Pill
Benchmark SRAM usage, Flash usage, inference latency, and power consumption
Compare EdgeFlex AI against a suitable baseline
Optimize the runtime based on measured results
Extend the framework toward other ARM Cortex-M platforms and TinyML applications