DTC_hardware

Inspiration

The challenge: take a stream of price packets over UART and decide BUY, SELL or hold for two items, using only an FPGA with no host software. We wanted to see how small and fast we could make it, since LUT count and latency are both scored.

What it does

Our Tang Nano 20K design receives 8-byte requests at 115200 baud and routes each item by its ID (0x11 or 0x22). For each item it keeps an independent 16-price moving-average window, compares the previous and current price against the old and new averages, and detects BUY/SELL crossings. It then sends back exactly 8 bytes: the echoed index and items, the actions in the same slot order, and a zero reserved field. Index 0 starts a fresh session by itself. All parsing, state, computation and response generation happen on the FPGA.

How we built it

The design is written in VHDL with no starter code. A UART receiver and transmitter feed a small microcoded datapath: ROM tables (generated from a Python reference model) hold the control sequence, timing and ALU operations, and block RAM stores each item's window, rolling sum, previous price and last action. Local tests used the organizers' quick and robust UART scripts plus our own full-range and stress scripts (random seeds, edge-case price patterns).

Challenges we ran into

• The BL616 USB-serial bridge can drop bytes if the FPGA sends response bytes back-to-back, so we added idle time between response bytes without hurting latency.
• Keeping exact floor-division averaging and the crossing rules correct across full 16-bit price ranges, warm-up, and slot swapping.
• Shrinking the logic: the first version used 298 LUTs. We optimized it down to 118, then to 0.

Accomplishments that we're proud of

• 84/84 scored packets and 168/168 actions correct on the board, with 0 timeouts.
• Average round-trip latency of 16.927 ms (the reference is 16.626 ms).
• 0 LUTs and 0 ALUs, against the 542-LUT reference. The logic runs from block RAM (41/46 BSRAM), with only 8 registers.

What we learned

Moving logic out of LUT fabric into ROM-based microcode can cut LUT usage dramatically. We also learned how much the USB-serial bridge affects UART reliability and latency, and that a software reference model is essential for verifying hardware.

What's next for DTC

Reduce BSRAM use to leave headroom, trim latency further, and add a VHDL simulation testbench so the design can be checked without the board.

Final GitHub Submission Repository: https://github.com/ItzSt0rmz/GQH26-DTC Final Commit SHA: 80c0466ecb7769698be3fbf27ac0814176d1c796

Built With

• python
• vhdl