Cross-Entropy

Inspiration

Quantum computers have enormous potential, but their practical applications remain limited by noise. Unlike classical bits, quantum states are extremely sensitive to environmental disturbances, imperfect gates, and measurement errors. Even small errors can accumulate rapidly during computation.

We were inspired by one of the central challenges in quantum computing: how can we reliably preserve quantum information when the physical hardware itself is unreliable?

For the DuQuantum IQM Challenge 2026, we decided to explore this question by implementing a surface-code quantum memory on IQM's 20-qubit Garnet quantum processor. Rather than relying entirely on simulations, we wanted to build a complete error-correction pipeline, execute it on real superconducting hardware, and investigate whether hardware-aware optimizations could improve logical memory performance.

What it does

Cross-Entropy implements a distance-3 rotated surface code on IQM Garnet, using 17 physical qubits to encode and protect one logical qubit.

The implementation consists of nine data qubits and eight ancilla qubits. The ancillas repeatedly measure four X-type and four Z-type stabilizers, which detect phase-flip and bit-flip errors without directly revealing the encoded quantum information.

For example, a Z-type stabilizer takes the form

$$ S_Z = Z_1 Z_2 Z_3 Z_4. $$

Its measurement reveals the parity of four data qubits. By tracking changes in these stabilizer measurements across successive rounds, we can identify likely physical errors.

We use a minimum-weight perfect matching (MWPM) decoder to infer the most likely error configuration and correct the logical measurement outcome in software.

By repeating the experiment for different numbers of stabilizer rounds, we estimate the logical failure probability:

$$ P_L(r)=\frac{\text{Number of decoded logical failures}}{\text{Total shots}}. $$

We then fit the logical error rate per round, $\epsilon_L$, using

$$ 1-2P_L(r)=(1-2\epsilon_L)^r. $$

Our implementation supports both logical X-memory and Z-memory experiments and investigates how dynamical decoupling can improve quantum information storage.

How we built it

We developed an end-to-end quantum error-correction pipeline using Python, Stim, Qiskit, IQM Resonance, and PyMatching.

Surface-code generation

We used Stim to generate rotated surface-code circuits with configurable code distance, stabilizer rounds, and memory basis. Each circuit includes the stabilizer measurement schedule, detection events, and logical observable.

We translated these circuits into Qiskit and adapted them to Garnet's native operations. We also implemented measurement-based conditional resets, allowing ancilla qubits to be reused across successive error-correction rounds.

Hardware-aware qubit mapping

One of our main objectives was to eliminate unnecessary SWAP operations, which introduce additional gate errors.

We modeled the surface-code circuit and Garnet's physical connectivity as graphs. We then searched for assignments in which every required two-qubit interaction corresponded to an existing hardware connection.

This produced four valid zero-SWAP placements.

We incorporated Garnet's calibration data, including single-qubit, CZ-gate, and readout error metrics, into a hardware-informed noise model.

Using Monte Carlo simulations and simulated annealing, we searched for placements minimizing the decoded logical failure probability. We evaluated candidate mappings with independent validation samples rather than relying solely on noisy optimization estimates.

Error decoding and statistical analysis

After running circuits on Garnet, we reconstructed the measurement records, extracted detection events, and used PyMatching to predict logical corrections.

We measured logical failure probabilities across different round counts, calculated confidence intervals, and fitted per-round logical error rates.

Dynamical decoupling

We also tested XX dynamical decoupling, which introduces refocusing pulses during idle periods to mitigate certain forms of decoherence.

We compared circuits with dynamical decoupling enabled and disabled, separately testing X-memory and Z-memory across one, two, and three stabilizer rounds.

Challenges we ran into

Mapping an abstract circuit onto real hardware. Garnet's qubits have restricted connectivity, meaning that not every pair can directly interact. Finding a placement supporting all surface-code stabilizer interactions without routing SWAPs required graph-based optimization and careful verification of the compiled circuits.

Implementing reliable syndrome extraction. Repeated stabilizer measurements require precise control over ancilla preparation, entangling-gate ordering, measurement records, and conditional resets. Incorrect measurement indexing or detector definitions can invalidate the decoder even when the quantum circuit executes successfully.

Accounting for realistic hardware noise. Our initial calibration-informed simulations modeled gate and readout errors but did not fully capture idle-time decoherence, leakage, or correlated errors. Real hardware performance was substantially different from our initial simulation predictions.

Interpreting noisy experimental results. Estimating logical error rates requires more than counting incorrect measurements. Limited sample sizes, preparation and readout errors, and hardware drift can complicate statistical interpretation. In particular, our five-round follow-up showed that a constant per-round error model did not adequately explain all the experimental data.

Accomplishments that we're proud of

Our biggest accomplishment was successfully implementing and running a complete surface-code quantum memory experiment on a real quantum processor.

Some highlights include:

• Zero routing SWAPs: We mapped all 17 circuit qubits onto Garnet's native connectivity, requiring 24 CZ gates per stabilizer round.
• Calibration-informed placement optimization: Our three-round simulations reduced estimated Z-memory logical failures from 5.60% to 5.18% and X-memory failures from 6.47% to 6.20%.
• Complete error-correction pipeline: We implemented syndrome extraction, MWPM decoding, logical error analysis, and statistical confidence intervals.
• Experimental improvement with dynamical decoupling: For three-round X-memory experiments, XX dynamical decoupling reduced logical failures from 43.8% to 20.8%, approximately a 53% relative reduction.
• Extended hardware testing: We performed five-round experiments, obtaining logical failure probabilities of 43.8% for X-memory and 39.0% for Z-memory with XX dynamical decoupling.

The dynamical-decoupling result was especially interesting because it demonstrated that optimizing how qubits behave during idle periods can significantly affect logical error-correction performance.

What we learned

We learned that quantum error correction is not purely a theoretical coding problem. Successful implementation requires close integration between quantum information theory, classical algorithms, hardware architecture, and statistical analysis.

A mathematically correct surface-code circuit can perform poorly if its operations are inefficiently mapped onto physical qubits. Similarly, a circuit that appears reliable in simulation may behave very differently on real hardware.

We gained practical experience with stabilizer measurements, syndrome extraction, graph-based qubit placement, Monte Carlo noise modeling, simulated annealing, and minimum-weight perfect matching.

Most importantly, we learned that hardware-aware optimization can be just as important as the error-correcting code itself. Our dynamical-decoupling experiments demonstrated that even without changing the underlying code, physical-level improvements can substantially reduce observed logical failures.

We also learned the importance of uncertainty quantification and experimental validation. An optimization is only meaningful if its improvement can be distinguished from statistical fluctuations and hardware variability.

What's next for Cross-Entropy

Our next step is to improve the fidelity of our hardware noise model by incorporating realistic idle-time decoherence, qubit leakage, and correlated errors.

We also want to explore more advanced circuit optimizations, including improved gate scheduling, single-qubit gate simplification, calibration-weighted decoding, and pulse-level techniques where supported.

Another direction is studying longer error-correction sequences and investigating how logical error rates evolve over time, particularly when the assumption of a constant per-round error rate breaks down.

Finally, we hope to extend our implementation to larger surface-code distances on compatible hardware and compare encoded quantum memory against an unencoded physical-qubit baseline.

Our long-term goal is to better understand how quantum error correction can transition from a theoretical framework into a practical tool for building reliable quantum computers.

Built With

• qiskit