Convolutional Trials on FPGA with PYNQ-Z2 Board

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  Edges detection convolution II

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  Edges detection convolution I

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  PYNQ-Z2 board

Our initial goal was to implement real-time image processing leveraging hardware acceleration. However, we faced significant challenges early on due to the lack of essential hardware components, including an Ethernet cable and an SD card, both of which were critical for our setup. In an attempt to proceed, we shifted to using UART communication, but this resulted in substantial performance issues and limited throughput. Despite our efforts, we were unable to achieve the real-time performance we had originally envisioned.

With half of the hackathon time already spent, we decided to pivot towards a different approach: benchmarking a 2D convolution algorithm. Specifically, we focused on comparing the performance of a software-based implementation running on the PYNQ PS (Processing System) against a hardware-accelerated version. This shift allowed us to concentrate on a more manageable task, but time constraints meant that we only managed to develop a functional software implementation of the convolution algorithm. Unfortunately, we were unable to validate the hardware acceleration portion due to time limitations.

In the repository, you’ll find a branch called accel_trial, which contains an early version of a simple hardware accelerator. While we successfully implemented a testbench in Vivado to verify basic functionality, we couldn’t fully integrate or validate the hardware in a hardware-software co-design context.

Although we were unable to complete the final goal within the hackathon timeframe, we gained invaluable insights into the development process. In hindsight, some of our initial objectives may have been overly ambitious, but we are proud of the progress made and the lessons learned throughout this challenging and rewarding experience.

Built With

• c
• opencv
• python
• soc
• vhdl