CONVEY

Open, patient-isolated 8-channel EEG, EMG and ECG acquisition board around the ADS1299, powered by a USB power bank, for a fraction of the price.

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Inspiration

Since I was a kid I have taken things apart to see how one chip talks to another. I never studied electrical engineering, but the hobby stayed. When I looked at the hardware people use for biosignal research (EEG, EMG, ECG), the entry ticket was an OpenBCI Cyton: about PHP 70,000 for eight channels and PHP 140,000 for sixteen here in the Philippines, before shipping, import fees and electrodes. For students, hobbyists and independent researchers that is a wall. CONVEY is my attempt to make that first step accessible, and to understand what goes into building the instrument itself: the acquisition chain, the isolation, the synchronisation and the verification.

The name is the job description. To convey is to carry something from one place to another and to communicate a message or express what is felt. The body already produces those messages as tiny electrical signals in the brain, the heart and the muscles; the board carries them across the isolation barrier, cleanly and safely, so they can be read and made sense of. CONVEY moves the signal from the body to the screen.

What it does

CONVEY is an open-hardware, general-purpose biosignal acquisition board. One 64 x 64 mm four-layer PCB records EEG, surface EMG or ECG: eight 24-bit differential channels around the TI ADS1299, with sample rate (250 SPS to 4 kSPS), gain, reference routing and bias drive all set over SPI. It is patient-isolated (an 8 mm copper-free barrier across all four layers, a medical-grade isolated DC/DC converter and reinforced 5000 V_RMS digital isolators), powered from an ordinary 5 V USB power bank through an eFuse with over-voltage lock-out, and it suppresses 50/60 Hz pickup in hardware with an active bias drive instead of relying on a notch filter in software. A six-axis IMU is clock-locked to the ADC's own oscillator (2.048 MHz divided by 64 = 32.000 kHz), so movement and biosignal share one time base and motion artefacts can be subtracted rather than guessed at. Any microcontroller drives it over a 15-pin header; a reference ESP32-S3 firmware and a Python plotter are included. Against the OpenBCI Cyton, which uses the same ADS1299, CONVEY adds an isolation barrier that does not depend on battery power, a wired 4 kSPS path instead of a 250 Hz wireless link, a six-axis IMU on the ADC's clock instead of a 25 Hz accelerometer, TVS protection on every input and a host-agnostic interface; the Cyton has wireless, SD logging and a mature software ecosystem, and it exists (tech report Section 2, Table 1).

How we built it

Netlist first: the canonical net list is a table and the first KiCad schematic was generated from it; every later hand edit was gated by re-exporting the netlist and re-running the board verifier against it, so the specification, the schematic and the board were kept consistent by tooling. Every part value traces to a datasheet page (document number, revision and SHA-256 recorded). Layout in KiCad 10: 146 components, 99 nets, 0.127 mm minimum trace, and a rule area that forbids copper in the barrier band on every layer. Routed with freerouting for the bulk and finished by hand to a written track-width convention. Then the gates: KiCad DRC with zero errors, a 56-check verifier that re-derives geometry, barrier, netlist-to-board consistency, 3D resolution and width rules from the files, and a second tool that parses the actual Gerber and drill files to prove the barrier is empty. A two-pass adversarial design review was run against rendered datasheet figures ("assume everything is wrong until proven right"); every finding was fixed and re-gated. The JLCPCB package (Gerbers, BOM with LCSC numbers checked live for stock, pick-and-place) is ready to upload. Finally a reference ESP32-S3 firmware (ADS1299 and IMU bring-up, DRDY-driven streaming) that compiles today, plus a live plotter.

Challenges we ran into

  • The physics of the barrier: 8 mm of creepage across a 64 mm board dictates the whole floorplan. Some obvious connector groupings are impossible by design and had to be explained rather than forced.
  • A schematic that lied: a mismatched root UUID silently broke new wire connectivity for weeks. It was found by one-variable bisection on stripped copies.
  • A tool that corrupts: a third-party KiCad automation plug-in re-serialised KiCad 10 files into something unloadable. We switched to surgical, snapshot-guarded edits with netlist-diff gates.
  • A 3D model that kept flipping: four times the oscillator and IMU models turned upside down at KiCad exit. The root cause was our own verifier expecting the wrong rotation and a library sync resurrecting it. The gate was fixed, the symptom was never the problem.
  • Datasheets that change the design: the IMU's production datasheet reversed the oscillator choice (2.097152 MHz to 2.048 MHz); the eFuse datasheet showed no reverse-polarity protection, so the diode stayed. Reading the primary source every time paid for itself.
  • Parts that exist: two "in stock" resistors from a community mirror were out of stock. Stock is now read live. Oscillator and TVS suffixes are named to the letter because the wrong suffix is a different part.
  • No physical board in time: fabrication, assembly and shipping to the Philippines take two to three weeks, longer than the event. We say so up front and show the evidence a prototype would stand on.

Accomplishments that we're proud of

A fab-ready design with zero DRC errors, 56 of 56 automated gates, the isolation barrier verified on the Gerbers, ERC clean, and a two-pass adversarial review closed, all re-runnable from the repo. A complete JLCPCB package with live-verified parts. And a design that is genuinely general-purpose: the same eight inputs are an EEG 10-20 subset, an ECG lead set or a facial EMG montage with only a cable change.

What we learned

Verify connectivity, never fill presence. Design to the netclass clearance, never to the board minimum. A check that has never failed is still unproven. Read pin tables from the rendered figure; a second-hand summary once misstated an entire datasheet. And it is never too late to become the person you thought you would be in some alternate universe; you can still build the thing you were always curious about.

What's next for CONVEY

Order the first article the week after Reverie Hacks 2026 and run the ten-step bring-up plan (every step already has its expected value: barrier resistance, ID register, DRDY rate, shorted-input noise floor, IMU clock lock). Publish the measured noise floor in the repository. Then the next board from the review notes, an enclosure and an ESP32-S3 carrier for an untethered wearable, and a classroom kit with the three montage cables. Open hardware (CERN-OHL-S), open firmware (MIT).

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