Inspiration
Qubits are fragile. Every gate, every idle moment and every measurement can corrupt them, and a useful computation needs millions of operations. Quantum error correction spreads one logical qubit across many physical qubits, so errors can be spotted and fixed before the information is lost. We wanted to see how that works on a real chip.
What it does
Coherence runs a distance-3 rotated surface code (9 data qubits and 8 helper qubits) on IQM Garnet. The helper qubits repeatedly check their neighbours' parity without reading the data. We decode the results offline and fit the logical error rate per round, \(\varepsilon_L\), using
$$2P = 1-(1-2\varepsilon_L)^n$$
where \(P\) is the logical error probability after \(n\) rounds. On hardware the code logs \(\varepsilon_L \approx 0.07\)–\(0.10\) per round, depending on the day and the settings.
How we built it
- Circuit. Stim generates the code. Because IQM chips have no mid-circuit reset, we rewrote every detector to compare a measurement with the one two rounds earlier.
- Layout. A subgraph search over Garnet's 30 couplers shows exactly one SWAP-free placement exists. Our Qrisp pass pins the code there, and every circuit we send is checked for 24 CZ gates per round, 0 SWAPs and no gate off a coupler.
- Runs. Qrisp's
DetectorExperimentsent jobs through IQM Resonance. We ran 1 to 5 rounds with dynamical decoupling (DD) on and off, against a naive layout, and repeated the baseline the next day. - Decoding. PyMatching decodes the detection events, with bootstrap confidence intervals on the fit.
- Analysis. We recorded calibration snapshots around every run and built a calibration-based noise model, a hot-spot map and an error-budget ablation.
Challenges we ran into
- The no-reset detector rewrite is easy to get wrong. A naive swap of reset for plain measurement produces detectors that aren't deterministic, so we added a negative-control test.
- IQM's default compiler crashed on our detector markers, so we wrote our own transpile pass.
- Only one SWAP-free patch exists on Garnet, so our planned patch scan became a layout-cost comparison.
- The chip drifted. The same experiment gave different results a day later.
- One decay rate fits poorly, because round 1 behaves differently from later rounds.
Accomplishments that we're proud of
- A provably zero-SWAP layout. A naive layout needed 54 to 93 extra CZ gates and had a one-round logical error of 26%, against 4%.
- A pipeline that is checked end to end. Verification tests cover the circuit, the no-reset rewrite, the layout and a noiseless dry run through IQM's own converter. Every job saves its raw counts, so every result can be rebuilt.
- DD cut the logical error per round from 0.104 to 0.065 over rounds 1 to 3, measured with DD on and off interleaved.
- The next-day repeat improved from 0.102 to 0.070 even though CZ error roughly doubled. That points to readout and idling as the main limit.
What we learned
- Layout matters more than any single tuning knob.
- Hardware drifts, so any logical error rate belongs to one calibration set.
- Gate and readout errors from calibration alone predict an error rate 7 to 8 times lower than we measured. The rest comes from effects the calibration numbers don't capture, and idling during mid-circuit readout is our best guess.
- A distance-3 code on this chip doesn't yet protect the logical qubit. We didn't measure a single-physical-qubit baseline, so we can't claim it beats one.
What's next for Coherence - IQM Challenge
- CZ noise had the largest effect in our model, which is something we can further explore.
- Weight the decoder with calibration data instead of a uniform 0.3% prior.
- Add idle noise to the simulation, to test the idling explanation directly.
- Measure a physical-qubit baseline for comparison.
- Run on other chips and larger distances, and try pulse-level compilation.
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