Coal

Inspiration

Chip design remains one of the most manual and fragmented processes in the field of engineering; the various stages including writing the RTL, simulating it, synthesizing it, placing and routing it, and checking the physical layout take place in separate tools that don't communicate with each other, and at each transfer a human has to manually detect and catch any errors. That's why we asked ourselves: what if an AI agent could take over the entire process itself, in the same way that a senior chip engineer does by writing, verifying, fixing, and iterating rather than just producing the code once and then hoping it's correct?

What it does

Coal is an autonomous AI agent which, on its own, takes a simple English description of a chip and guides it through the entire RTL-to-GDSII design process. It generates the Verilog or VHDL code, carries out simulation and verification of the logic, synthesises the design using an open PDK, performs placement and routing of the physical design, and produces the actual silicon layout detecting any failures at each verification stage and correcting its own work before proceeding to the next one.

How we built it

Coal is constructed as a tool-calling agent loop, with an NVIDIA model serving via the Nebius Token Factory acting as the orchestrator and sending out calls to a series of open-source EDA tools each of which is packaged as a separate tool that the agent can call upon:

• RTL generation & linting Verible
• Simulation Icarus Verilog / Verilator, with waveform output viewed in GTKWave
• Synthesis Yosys, against the open sky130 PDK
• Floorplanning, placement & routing OpenROAD (via OpenLane 2)
• Physical layout / GDSII Magic VLSI
• DRC/LVS verification Magic + Netgen
• 2D chip visualization KLayout

Each stage acts as a strict verification checkpoint, not merely a step; the agent must complete the simulation before moving on to synthesis, must pass the synthesis checks before proceeding to place and route, and must pass the DRC/LVS before the design can be regarded as complete.

Challenges we ran into

The fundamental difficulty was in using tools that were not intended to communicate with an LLM agent instead of simply giving the model new prompts, we had to interpret the raw logs from the EDA tools (such as synthesis reports, DRC violations, and timing errors) so that the model could take action on them. We also needed to clearly define the scope: by "any chip" we mean any digital design that can be synthesised using an open PDK, not any analog or advanced-node silicon it was just as important to get this distinction right as it was to produce the code, and to communicate that distinction honestly.

Accomplishments that we're proud of

Getting a closed verification loop to work at all that is, having an agent which doesn't simply produce RTL once but instead notices when its own design fails and carries out iterations until it passes.

What we learned

Hardware verification is much more unforgiving than software when a layout fails DRC there is no such thing as "close enough". Because of this we have had to adopt a lot more strict tool-output parsing and gate-based agent logic than is normally required of a typical coding agent.

What's next for Coal

Features including timing closure feedback loops, support for a second PDK, and hierarchical multi-module designs.

Built With

• docker
• eda
• gtkwave
• icarus-verilog
• klayout
• llm-agents
• magic-vlsi
• nebius
• nvidia
• openlane
• openroad
• python
• tool-calling
• verilog
• vhdl
• yosys