BrainHack

• 

  this is not the project.

Inspiration

The language is interesting and small. It suits well a RISC architecture. I like hardware.

What it does

Natively interprets brainfuck (using logic gates and memory ics)

How I built it

A lot of verilog and clock diagrams.

Challenges I ran into

A lot of verilog. Also, it's harder than expected. Also, sleep deprivation doesn't help.

Accomplishments that I'm proud of

The design. Also, it works. That's cool.

What I learned

Not to do it again. But it was cool.

What's next for BrainHack

Get it on an FPGA. I want to see some blinking LEDs. Also the code might do with some cleaning up.

Built With

• altera
• quartus
• verilog