The huge potential impact of the optimal physical layout design on the performance of Quantum chips is very well known, yet, Unlike semiconductor physical design methodology, the Quantum architecture design & Quantum physical layout design lacks enough research & development. The lack of a comprehensive & integrated EDA environment for the Physical layout design of quantum chips is the main reason behind low research in this area. Thanks to IBM, we now have access to QISKIT METAL an open-source Q-EDA tool for the purpose of Physical layout design of Superconducting based Quantum Chips. Our main goal is to physically design various building blocks of Quantum chips and make them available for the open-source community as Hard IPs.
What it does
Hard IPs are physically hardened re-usable modules. To start off, we have physically implemented 'modified R2', R3, R4, R5 - LNN-based architectures of superconducting Quantum chips on QISKIT Metal and achieved practical performance results. As they're available for the open-source community, any individual or a company can parametrize & instantiate them as a whole or as part of their bigger project depending on their requirements and generate GDS and eventually manufacture the Quantum Chip at the foundry.
How we built it
The physical design process involved numerous iterations of programming the physical layout of the Circuit in QISKIT METAL using Python3.0 and optimizing the area & cross-talk and analyzing the results using QISKIT Metals renderers & used qiskit metals integration with Ansys HFSS to re-iterate and achieve desired Transmon qubits resonant frequency, anharmonicity, Chi,. Relaxation(T1) & de-coherence(T2) time etc.
Challenges we ran into
Challenges involved, going through numerous iterations to achieve desired specifications (i.e Transmon qubits resonant frequency, anharmonicity, Chi, Relaxation(T1) & de-coherence(T2) time, area, connectivity, etc.) within the provided time constraint. Reducing the cross-talk and at the same time keeping the design compact was a huge challenge. Also, encountered a ton of manufacturability-related errors & warnings. QISKIT Metal being a new Q-EDA tool, adapting to it was a challenge in itself. Integrating Ansys analysis tools to QISKIT Metal using renderers, integration with ANSYS Electronics suite, figuring out which models and objects are compatible as of time of writing.
Accomplishments that we're proud of
We are proud of keeping the design compact and implementing multiple LNN-based architectures to achieve reasonable resultant performance.
What we learned
Gained experience in using QISKIT METAL & Ansys analysis tools using in-built QISKIT Metal renderers. Learned various Quantum physical design constraints and techniques to fix/optimize them i.e Techniques to reduce cross-talk by increasing gap between routes, techniques to increase relaxation(T1) & de-coherence(T2) times using cavity resonators and avoiding direct Qubit energy leakage, techniques to achieve desired frequency range and anharmonicity by modifying the Transmon Qubits Pad dimensions & Josephson Junctions dimensions to vary capacitance & inductance of the Qubit respectively.
What's next for the Physical Layout design of Quantum chips on QISKIT Metal
To physically design even more optimized building blocks of Quantum circuits based on various architectures and thus increase the Hard IPs database/portfolio horizontally based on diverse sets of architectures and designs. Considering early development stage of QISKIT Metal, currently it has certain limitations like in-ability to implement 3D physical design structures etc, due to which, we couldn't implement R1-LNN architecture i.e the fully connected architecture. So, as QISKIT Metal eveolves to include the 3D Physical Structures, we will work to update our portfolio with R1-LNN architectures as well. And, thus eventually improve the Quantum hardware performance.